A field-programmable gate-array system for evolutionary computation

  • Tsutomu Maruyama
  • Terunobu Funatsu
  • Tsutomu Hoshino
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 1482)


In evolutionary computation, evolutionary operations are applied to a large number of individuals (genes) repeatedly. The computation can be pipelined (evolutionary operators) and parallelized (a large number of individuals) by dedicated hardwares, and high performance are expected. However, details of the operators depend on given problems and vary considerably. Systems with field programmable gate arrays can be reconfigured and realize the most suitable circuits for given problems. In this paper, we show that a hardware system with two FPGAs and SRAMs can achieve 50130 times of speedup compared with a workstation (200MHz) in some evolutionary computation problems. With a larger system, we believe that we can realize more than 10 thousands of speedup.


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Copyright information

© Springer-Verlag Berlin Heidelberg 1998

Authors and Affiliations

  • Tsutomu Maruyama
    • 1
  • Terunobu Funatsu
    • 1
  • Tsutomu Hoshino
    • 1
  1. 1.Institute of Engineering MechanicsUniversity of TsukubaIbarakiJapan

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