Speed optimization of the ALR circuit using an FPGA with embedded RAM: A design experience

  • Sameh Asaad
  • Kevin Warren
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 1482)


The Active Line Repair (ALR) circuit is a specialized circuit to overcome some of the manufacturing imperfections in high resolution flat panel displays. In this paper, the design of the ALR circuit is presented. Speed bottlenecks for an FPGA-based implementation are identified and optimization alternatives are discussed. Results stress the importance of data representation and the match to the underlying hardware resources such as embedded RAM blocks. The optimized circuit runs at 63 MHz system clock, achieving a 40% speedup over the original design.


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Copyright information

© Springer-Verlag Berlin Heidelberg 1998

Authors and Affiliations

  • Sameh Asaad
    • 1
  • Kevin Warren
    • 1
  1. 1.IBM T. J. Watson Research CenterYorktown HeightsUSA

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