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Speed optimization of the ALR circuit using an FPGA with embedded RAM: A design experience

  • Sameh Asaad
  • Kevin Warren
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 1482)

Abstract

The Active Line Repair (ALR) circuit is a specialized circuit to overcome some of the manufacturing imperfections in high resolution flat panel displays. In this paper, the design of the ALR circuit is presented. Speed bottlenecks for an FPGA-based implementation are identified and optimization alternatives are discussed. Results stress the importance of data representation and the match to the underlying hardware resources such as embedded RAM blocks. The optimized circuit runs at 63 MHz system clock, achieving a 40% speedup over the original design.

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References

  1. 1.
    S.L.Wright et al.: Active Line Repair for Thin-Film-Transistor Liquid-Crystal Displays Research Report RC 20779, IBM Research Division, March 24, 1997.Google Scholar
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    Altera Corporation: 1997 Data Book Altera Corp. 101 Innovation Drive, San Jose, CA 95134 http://www.altera.com/html/literature/literature.htmlGoogle Scholar
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    Synopsys Corporation: FPGA Express User's Guide v1.2, September 1996 Synopsys, 700 East Middlefield Road, Mountain View, CA 94043 http://www.synopsys.comGoogle Scholar
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    Altera Corporation: Max Plus II Development Software Users Manual v8.1, Altera Corp. 101 Innovation Drive, San Jose, CA 95134 http://www.altera.com/html/literature/literature.htmlGoogle Scholar
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    Ellen M. Sentovich et al: SIS: A system for Sequential Circuit Synthesis Electronics Research Laboratory Memorandum No. UCB/ERL M92/41, University of California at Berkeley, CA 94720, May 1992 ftp://ic.eecs.berkeley.edu/pub/Sis/SIS_paper.ps.ZGoogle Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 1998

Authors and Affiliations

  • Sameh Asaad
    • 1
  • Kevin Warren
    • 1
  1. 1.IBM T. J. Watson Research CenterYorktown HeightsUSA

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