Abstract
Floorplanning is a crucial step in the physical design flow for FPGAs. In this paper, we use min-cut based successive bipartitioning to floorplan circuits for application to FPGAs. The primary motivation of this work is reduction of execution lime required to accomplish the floorplanning step of device mapping. Our method includes clustering to enhance circuit performance and terminal propagation to reduce total wire length and enhance circuit routability. The floorplanner is intended to take predefined macro based designs as input. Using the Xilinx xc4000 series of FPGAs as the target architecture, we have demonstrated effective and fast floorplanning on a collection of designs.
This research is partially supported by contract number F33615-96-C1912 from Wright Laboratory of the US Air Force and a grant from Lucent Technologies
Access this chapter
Tax calculation will be finalised at checkout
Purchases are for personal use only
Preview
Unable to display preview. Download preview PDF.
References
C. Fiduccia and R. Mattheyses, “A Linear time Heuristic for Improving Network Partitions”, Proc. of DAC, pp.175–181, June 1982.
M. Breuer, “A class of min-cut placement algorithms”, Proc. of DAC, pp. 284–290, 1980.
A. E. Dunlop and B. W. Kernighan, “A Procedure for Placement of Standard-Cell VLSI Circuits”, IEEE Transactions on Computer-Aided Design, pp. 92–98, January 1985.
J. M. Emmert and D. K. Bhatia, “Fast Placement Using TABU Search for Total Wire Length Minimization”, University of Cincinnati, ECECS Technical Report, 1998.
Jianzhong Shi, Akash Randhar and Dinesh Bhatia “Macro block based FPGA Floorplanning” Proc. of Intl. Conf. on VLSI Design, January 1997.
J. Shi and D. Bhatia, “Performance Driven Floorplanning for FPGA Based Designs” Proc. of ACM Symposium on Field Programmable Gate Arrays, February 1997.
A. Mathur and C.L. Liu, “Compression-Relaxation: A New Approach to Timing Driven Placement for Regular Architectures” IEEE Transactions on CAD of Integrated Circuits and Systems, pp. 597–608, June 1997.
A. Randhar, “Macro Based Floorplanning for FPGAs” Thesis: University of Cincinnati, December 1997.
C. Sechen “Chip Planning, Placement, and Global Routing of Macro/Custom Cell integrated Circuits Using Simulated Annealing” in Proc. of DAC, pp. 73–80, June 1988.
A. Subramaniam and D. Bhatia “Timing Driven Placement for Logic Cell Arrays” University of Cincinnati, ECECS Technical Report, 1994.
D.F. Wong and C.L. Liu “A new method for floorplan design” Proc. of DAC, pp. 101–107, 1986.
www.xilinx.com.
Author information
Authors and Affiliations
Editor information
Rights and permissions
Copyright information
© 1998 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Emmert, J.M., Randhar, A., Bhatia, D. (1998). Fast floorplanning for FPGAs. In: Hartenstein, R.W., Keevallik, A. (eds) Field-Programmable Logic and Applications From FPGAs to Computing Paradigm. FPL 1998. Lecture Notes in Computer Science, vol 1482. Springer, Berlin, Heidelberg. https://doi.org/10.1007/BFb0055240
Download citation
DOI: https://doi.org/10.1007/BFb0055240
Published:
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-64948-9
Online ISBN: 978-3-540-68066-6
eBook Packages: Springer Book Archive