CAD system for ASM and FSM synthesis

  • Samary Baranov
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 1482)


For hardware realization of computer programs (for the realization of software as hardware) it is very important to represent, to transform and to synthesize very complex Finite State Machines (FSM). This work contains the first report about CAD system Synthesis 1 for design of FSMs with hardly any constraints on their size, that is, the number of inputs, outputs and states. Synthesis 1 implements automatically various transformations of an Algorithmic State Machine (minimization, composition, decomposition etc.) and synthesis of FSM's logic circuit as (a) multilevel circuit with gates from a predefined library; (b) with standard LSI and VLSI circuits without memory, such as PLA(s,t,q) — programmable logic arrays with s inputs, t outputs and q horizontals; (c) with standard LSI and VLSI circuits with memory, such as PLAM(s,t,q,r) — programmable logic arrays with s inputs, t outputs, q horizontals and r memory elements; (d) matrices circuits on the chip with a minimization of the chip area; (e) with LUTs (Look-Up-Tables) for FPGA technology.


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    Baranov, S., Bregman, L.: Synthesis of automata from elements with given constraints on their complexity. Journal of Microcomputer Applications. 17, (1994) 227–237CrossRefGoogle Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 1998

Authors and Affiliations

  • Samary Baranov
    • 1
  1. 1.Computer System DepartmentCenter for technological Education HolonHolonIsrael

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