An optimized design flow for fast FPGA-based rapid prototyping

  • Jörn Stohmann
  • Klaus Harbich
  • Markus Olbrich
  • Erich Barke
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 1482)


In this paper, we present an optimized design flow to map Register-Transfer-Level (RTL) netlists onto multiple-FPGA architectures. Our FPGA-dedicated method fully exploits design structure by letting the basic design steps technology mapping, hierarchical partitioning, floorplanning and signal flow driven placement, interact. This efficiently reduces runtime and yields design implementations of higher performance and better resource utilization than published before.


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Copyright information

© Springer-Verlag Berlin Heidelberg 1998

Authors and Affiliations

  • Jörn Stohmann
    • 1
  • Klaus Harbich
    • 1
  • Markus Olbrich
    • 1
  • Erich Barke
    • 1
  1. 1.Institute of Microelectronic SystemsUniversity of HanoverHanoverGermany

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