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Acceleration of satisfiability algorithms by reconfigurable hardware

  • Marco Platzner
  • Giovanni De Micheli
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 1482)

Abstract

We present different architectures to solve Boolean satisfiability problems in instance-specific hardware. A simulation of these architectures shows that for examples from the DIMACS benchmark suite, high raw speed-ups over software can be achieved. We present a design tool flow and prototype implementation of an instance-specific satisfiability solver and discuss experimental results. We measure the overall speed-up of the instance-specific architecture that takes the hardware compilation time into account. The results prove that many of the DIMACS examples can be accelerated with current FPGA technology.

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Copyright information

© Springer-Verlag Berlin Heidelberg 1998

Authors and Affiliations

  • Marco Platzner
    • 1
  • Giovanni De Micheli
    • 1
  1. 1.Computer Systems LaboratoryStanford UniversityStanfordUSA

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