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Hardware algorithms for VLSI systems

  • Hiroto Yasuura
  • Shuzo Yajima
Chapter 3 VLSI Algorithms
Part of the Lecture Notes in Computer Science book series (LNCS, volume 163)

Abstract

In this paper, we discussed several problems in the design and analysis of hardware algorithms. The complexity theory of logic circuits and parallel computation will form the theoretical foundation of design and analysis of hardware algorithms which will become more important for large VLSI systems.

A formal description method of hardware algorithms will be proposed on a general model of parallel computation. Design tools for hardware algorithms will be developed such as a hardware description language, an automatic translation system from the language to circuits, a verification support system for algorithms, etc. Results of theoretical researches on the circuit complexity will play an important role in the development of these design tools.

Many hardware algorithms will be designed to various problems. Design methodologies such as systolic algorithms or BCA algorithms will become more important and be studied. Since a large system is a combination of software and hardware, a design methodology including design of both software and hardware algorithms will be discussed.

Keywords

Arithmetic Operation Turing Machine Computation Node Combinational Circuit Integer Multiplication 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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References

  1. [1]
    S.Yajima and H.Yasuura, “Hardware Algorithms and Logic Deign Automation — An Overview and Progress Report —“, Kyoto Univ. Yajima Lab. Research Rep. ER 82-01, June 1982. Also to appear in Lecture Notes on Computer Science, Springer-Verlag.Google Scholar
  2. [2]
    “Highly Parallel Computing“ Edited by L.S. Hayens, IEEE Computer, vol.15, no.1, pp. 7–96, Jan. 1982.Google Scholar
  3. [3]
    S.Yajima, H.Yasuura and Y.Kambayashi, “Design of Hardware Algorithms and Related Problems“, IECE Technical Rep. AL81–86, Dec. 1981 (in Japanese).Google Scholar
  4. [4]
    N. Tokura, “VLSI Algorithms and Area-Time Complexity“, Joho-Shori vol.23, no.3, pp.176–186, March 1982 (in Japanese).Google Scholar
  5. [5]
    C.A. Mead and L.A. Conway, “Introduction to VLSI Systems“, Addison-Wesley, Reading, Mass., 1980.Google Scholar
  6. [6]
    H.T.Kung, “The Structure of Parallel Algorithms“, Advanced in Computers, vol.19, Academic Press, 1980.Google Scholar
  7. [7]
    M.Foster and H.T.Kung, “The Design of Special-Purpose VLSI Chips“, IEEE Computer, vol.13, no.1, Jan. 1980.Google Scholar
  8. [8]
    S. Yajima and K. Inagaki, “Power Minimization Problems of Logic Network“, IEEE Trans. on Comput., vol.C-23, no.2, pp.153–165, Feb. 1974.Google Scholar
  9. [9]
    G.F.Pfister, “The Yorktown Simulation Engine: Introduction“, Proc. 19th Design Automation Conf.pp.51–54, June 1982.Google Scholar
  10. [10]
    H.G.Adshead, “Towards VLSI Complexity: The DA Algorithm Scaling Problem: Can Special DA Hardware Help?“, Proc. 19th Design Automation Conf. pp.339–344, June 1982.Google Scholar
  11. [11]
    R.A. Wood, “A High Density Programmable Logic Array Chip“, IEEE Trans. on Comput. vol.C-28, no.9, pp.602–608, Sept. 1979.Google Scholar
  12. [12]
    S. Yajima and T. Aramaki, “Autonomously Testable Programmable Logic Arrays“, Proc. FTCS-11, pp.41–43, June 1981.Google Scholar
  13. [13]
    T. Williams and K.P. Parker, “Design for Testability — A Survey“, IEEE Trans. on Comput., vol.C-31, no.1, pp.2–15, Jan. 1982.Google Scholar
  14. [14]
    J.E. Savage, “The Complexity of Computing“, Wiley-Interscience, Reading Mass., 1976.Google Scholar
  15. [15]
    C.D.Thompson, “Area-Time Complexity for VLSI“, Proc. 11th Symposium on the Theory of Computing, pp.81–88, May 1979.Google Scholar
  16. [16]
    R.P. Brent and H.T. Kung, “The Area-Time Complexity of Binary Multiplication“, JACM, vol.28, no.3, pp.521–534, July 1981.Google Scholar
  17. [17]
    A.V. Aho, J.E. Hopcroft and J.D. Ullman, “Design and Analysis of Computer Algorithms“, Addison-Wesley, Reading, Mass., 1974.Google Scholar
  18. [18]
    B.Chazelle and L.Monier, “Towards More Realistic Models of Computation for VLSI“, Proc. 11th Symposium on the Theory of Computing, pp.209–213, April 1979.Google Scholar
  19. [19]
    Z.M.Kedem and A.Zorat, “On Relations between Inputs and Communication/Computation in VLSI“, Proc. 22nd Symp. on the Foundations of Computer Science, pp.37–44, Oct.1981.Google Scholar
  20. [20]
    J.Vuillemin, “A Combinatorial Limit to the Computing Power of VLSI Circuits“, Proc. 21st Symp. on the Foundation of Computer Sience, pp.294–300, Oct. 1980.Google Scholar
  21. [21]
    H. Yasuura, “Theory of Complexity of Logic Functions and its Application to Logical Design of High-Speed Logic Circuits“, Trans. of the Information Processing Society of Japan, vol.21, no.4, pp.268–278, July 1980 (in Japanese).Google Scholar
  22. [22]
    A. Borodin, “On Relating Time and Space to Size and depth“, SIAM Jornal of Computing, vol.6, no.4, pp.733–744, Dec. 1977.Google Scholar
  23. [23]
    S.H. Unger, “Tree Realizations of Interactive Circuits“, IEEE Trans. on Comput., vol.C-26, no.4, pp.365–383, April 1977.Google Scholar
  24. [24]
    H. Yasuura, “Width and Depth of Combinational Logic Circuits“, Information Processing Letters, vol.13, no.4, 4,end, pp.191–194, 1981.Google Scholar
  25. [25]
    H. Yasuura and S. Yajima, “On the Area of Logic Circuits in VLSI“, Trans. of Institute of Electronics and Communication Engineers of Japan, vol.J65-D, no.8, Aug. 1982.Google Scholar
  26. [26]
    K. Hwang, “Computer Arithmetic:Principle, Architecture and Design“, John-Wiley & Sons, Reading, Mass., 1979.Google Scholar
  27. [27]
    L.B.Jackson, S.F.Kaiser and H.S.McDonald, “An Approach to the Implementation of Digital Filters,” IEEE Trans. Audio Electro., AU-16, Sept. 1968.Google Scholar
  28. [28]
    W.J. Stenzel, W.J. Kubitz and G.H. Garcia, “A Compact High-Speed Parallel Multiplication Scheme,” IEEE Trans. on Comput., vol.C-26, no.10, pp.948–957, Oct. 1977.Google Scholar
  29. [29]
    A.Karatsuba and Y.Ofman, “Multiplication of Multidigit Numbers with Computers“, Dokl. Akad. Nauk. SSSR, no.145, Feb. 1962.Google Scholar
  30. [30]
    C.S. Wallace, “A Suggestion for a Fast Multiplier“, IEEE Trans. on Electro. Comput., vol EC-13, no.1, pp.14–17, Feb. 1964.Google Scholar
  31. [31]
    N.Takagi, H.Yasuura and S.Yajima, “A High-Speed Array Multiplier Using Redundant Binary Representation,” to appear.Google Scholar
  32. [32]
    H.Yasuura and S.Yajima, “On the Delay Complexity of Square Rooting in Combinational Logic Circuits“, Tech. Rep. of IECEJ, AL79–29, July 1979.Google Scholar
  33. [33]
    H. Alt, “Square Rooting is as Difficult as Multiplication“, Computing, vol.21, pp.221–232, Jan.1979.Google Scholar
  34. [34]
    H. Yasuura and N. Takagi, “A High-Speed Sorting Circuit Using Parallel Enumeration Sort“, Trans. IECE, vol.J65-D, no.2, pp.179–186, Feb.1982 (in Japanese).Google Scholar
  35. [35]
    H. Yasuura, N. Takagi and S. Yajima, “The Parallel Enumeration Sorting Scheme for VLSI“, to appear in IEEE Trans. on Computer vol.C-31, no.12, Dec.1982.Google Scholar
  36. [36]
    H.Yasuura, “Hardware Algorithms for VLSI“, Proc. Joint Conf. of 4 Institutes Related on Electric Engineering, 34–4, Oct. 1981 (in Japanese).Google Scholar
  37. [37]
    H.Miyata, H.Yasuura and S.Yajima, “Hardware Algorithm for Large Integer Multiplication“, Tech. Rep. of IECEJ, AL81–99, Jan.1982 (in Japanese).Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 1984

Authors and Affiliations

  • Hiroto Yasuura
    • 1
  • Shuzo Yajima
    • 1
  1. 1.Department of Information Science Faculty of EngineeringKyoto UniversityKyotoJapan

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