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Channel routing with short wires

  • Compaction And Channel Routing
  • Conference paper
  • First Online:
VLSI Algorithms and Architectures (AWOC 1988)

Part of the book series: Lecture Notes in Computer Science ((LNCS,volume 319))

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Abstract

Channel routing is a fundamental problem in VLSI layout and has received much attention recently ([F],[MPS],[PL],[BBL],[BBBL],[GK]..). Unfortunately, most algorithms produce good layouts only with respect to the channel width, but not with respect to the length of the wires, which is a second important measure for the performance of the layout. Here, we consider the problem of routing a given channel with short wires. We show that our algorithms produce routings with minimum total wire length.

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Author information

Authors and Affiliations

  1. FB 10, Informatik, Universität des Saarlandes, 6600, Saarbrücken, West Germany

    Michael Kaufmann

  2. Department of Computer Science, The University of Texas at Dallas, P.O. Box 830688, FN 3.3, 75083 - 0688, Richardson, TX

    Ioannis G. Tollis

Authors
  1. Michael Kaufmann
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  2. Ioannis G. Tollis
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John H. Reif

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© 1988 Springer-Verlag Berlin Heidelberg

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Kaufmann, M., Tollis, I.G. (1988). Channel routing with short wires. In: Reif, J.H. (eds) VLSI Algorithms and Architectures. AWOC 1988. Lecture Notes in Computer Science, vol 319. Springer, New York, NY. https://doi.org/10.1007/BFb0040390

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  • DOI: https://doi.org/10.1007/BFb0040390

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  • Publisher Name: Springer, New York, NY

  • Print ISBN: 978-0-387-96818-6

  • Online ISBN: 978-0-387-34770-7

  • eBook Packages: Springer Book Archive

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