Channel routing with short wires
Channel routing is a fundamental problem in VLSI layout and has received much attention recently ([F],[MPS],[PL],[BBL],[BBBL],[GK]..). Unfortunately, most algorithms produce good layouts only with respect to the channel width, but not with respect to the length of the wires, which is a second important measure for the performance of the layout. Here, we consider the problem of routing a given channel with short wires. We show that our algorithms produce routings with minimum total wire length.
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- [BBBL]B. Berger, M. Brady, D. Brown, and F. T. Leighton: “Nearly Optimal Algorithms and Bounds for Multilayer Channel Routing”. Manuscript.Google Scholar
- [BBL]B. S. Baker, S. N. Bhatt, and F. T. Leighton: “An Approximation Algorithm for Manhattan Routing”. Proc. of the 15th Ann. ACM Symposium on Theory of Computing, pp. 477–486 (1983).Google Scholar
- [BB]M. Brady and D. Brown: “VLSI Routing: Four Layers Suffice”. MIT VLSI Conference 1984.Google Scholar
- [BP]D. Brown and F. P. Preparata: “Three-Layer Channel Routing of Multiterminal Nets”. Technical Report, Coordinated Science Lab., University of Illinois at Urbana-Champaign (Oct. 1982).Google Scholar
- [GK]S. Gao and M. Kaufmann: “Channel Routing of Multiterminal Nets”. Proc. of 28th Ann. Symposium on Foundations of Computer Science, pp. 316–325 (1987).Google Scholar
- [PL]F. P. Preparata and W. Lipski: “Optimal Three-Layer Channel Routing”. IEEE Trans. on Computers C-33, pp. 427–437 (1984).Google Scholar
- [RBM]R. L. Rivest, A. Baratz, and G. Miller: “Provably Good Channel Routing Algorithms”. Proc. CMU Conf. on VLSI, pp. 153–159 (Oct. 1981).Google Scholar
- [S]M. Sarrafzadeh: “On the Complexity of the General Channel Routing Problem in the Knock-Knee Mode”. to appear in IEEE Transactions on Computer-Aided DesignGoogle Scholar
- [SP]M. Sarrafzadeh and F. P. Preparata: “Compact Channel Routing of Multiterminal Nets”. Annals of Discrete Math., North Holland (Apr. 1985)Google Scholar
- [T]I. G. Tollis: “A New Algorithm for Wiring Layouts”. Proceedings of AWOC, (1988)Google Scholar