Novel design techniques for RNS systolic VLSI arrays
This paper presents novel design techniques for Residue Number System based systolic arrays for arithmetic computation useful in digital signal processing applications. Design of a 5-bit pipelined adder is explained with emphasis on the basic systolic cell design, use of clocks, pipeline techniques, simulation, and layout optimization. This pipelined adder can be used to build systolic multipliers, correlators, computational structures for DFT, etc.
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