Dynamically trace scheduled VLIW architectures
This paper presents a new architecture organisation, the dynamically !race scheduled VLIW (DTSVLIW), that can be used to implement machines that execute the code or current RISC or CISC instruction set architectures in a VLIW fashion, with backward code compatibility.
KeywordsVLIW Superscalar trace cache scheduling
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- J. E. Smith, S. Vajapeyam, “Trace Processors: Moving to Forth-Generation Microarchilectures” IEEE Computer, September 1997.Google Scholar
- J. A. Fisher, “The VLIW Machine: A Multiprocessor for Compiling Scientific Code”, IEEE Computer, pp. 45–53, July 1984.Google Scholar
- B. R. Rau, “Dynamically Scheduled VLIW Processors”, Proceedings of the 26th Annual Symposium on Microarchitecture, pp. 80–92, 1993.Google Scholar
- K. Ebcioglu, E. R. Altman, “DAISY: Dynamic Compilation for 100% Architectural Compatibility”, IBM Research Report RC20538, 82 pages. 1996.Google Scholar
- R. Nair, M. E. Hopkins, “Exploiting Instructions Level Parallelism in Processors by Caching Scheduled Groups”, IBM Research Report RC20628, 17 pages, 1996.Google Scholar
- S. Davidson, D. Landskov, B. D. Shriver, P. W. Mallelt, “Some Experiments in Local Microcode Compaction for Horizontal Machines”, IEEE Transactions on Computers, Vol. C30, No. 7, pp. 460–477, July 1981.xGoogle Scholar