Dynamically trace scheduled VLIW architectures

  • Alberto Ferreira de Souza
  • Peter Rounce
5. Posters
Part of the Lecture Notes in Computer Science book series (LNCS, volume 1401)


This paper presents a new architecture organisation, the dynamically !race scheduled VLIW (DTSVLIW), that can be used to implement machines that execute the code or current RISC or CISC instruction set architectures in a VLIW fashion, with backward code compatibility.


VLIW Superscalar trace cache scheduling 




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Copyright information

© Springer-Verlag Berlin Heidelberg 1998

Authors and Affiliations

  • Alberto Ferreira de Souza
    • 1
  • Peter Rounce
    • 1
  1. 1.Department of Computer ScienceUniversity College LondonLondonUK

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