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An integrated circuit for artificial neural networks

  • F. Castillo
  • J. Cabestany
  • J. M. Moreno
Hardware Implementations
Part of the Lecture Notes in Computer Science book series (LNCS, volume 540)

Abstract

A brief introduction is made of the Backpropagation algorithm and its parallelization in a proposed architecture. The main requirements of each of the architecture's processors is then elaborated and the final Integrated Circuit design presented. Each part of the processor is discussed separately: ALU, communications unit, memory and the control unit. The control unit is discussed with more detail by explaining how it performs when doing the emulation.

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VI. References

  1. [1]
    F.Castillo, J.Cabestany, "A VLSI Neural Net Architecture — A Proposal", Proc. Neuro-Nîmes'90.Google Scholar
  2. [2]
    F.Castillo, J.M.Moreno, J.Cabestany, "Digital VLSI Implementation of a Neural Processor", Proc. Melecon '91, Yugoslavia.Google Scholar
  3. [3]
    F.Castillo, P.Amengual, J.Cabestany, "A Sensibility Study of the Backpropagation Algorithm", Proc. ICANN'91, Helsinki.Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 1991

Authors and Affiliations

  • F. Castillo
    • 1
    • 2
  • J. Cabestany
    • 1
    • 3
  • J. M. Moreno
    • 1
    • 3
  1. 1.Dept. de Ingeniería ElectrónicaUniversidad Politécnica de CatalunyaSpain
  2. 2.E.U.P.Vilanova i la Geltrú Victor Balaguer s/nVilanova i la Geltrú
  3. 3.E.T.S.I. Telecomunicación Jordi Girona Salgado s/nBarcelona

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