Simulation of the MC88000 microprocessor system on a transputer network

Abstract

This project investigated the feasibility of building a General Purpose Architecture Simulator on an MIMD transputer network. In the course of this study an Occam2 simulation of the 88100 Reduced Instruction Set micro-processor was developed on an MIMD T800 transputer Surface. A T414 graphics processor with gfx.library functions was configured to produce a visual presentation of the architecture's internal data flows, indicating, for example, the occurrence of read after write conflicts and providing useful information for performance analysis. Work Bench Test programs were written in 88000 assembly code including a convolution test program composed of load/store, integer and floating point arithmetic and conditional/unconditional control transfer instructions, which ran at an average throughput of 8 MIPS. The simulation program was distributed over a grid of transputers using the software harness tiny in an attempt to speedup the simulation runtime. Simulated performance was verified by a direct comparison with the Vax accerelator, an 88000 system (courtesy of SUPERCOSMOS, Edinburgh Royal Observatory), that could run a deblender sampling algorithm 10 times faster than a Vax machine, with an estimated performance of 8 to 9 MIPs. The inherent flexibility supported by Occam2 and the transputer environment was evaluated by attempting to alter the 88000 system architecture. Further performance improvement was achieved by developing a Front Panel Display to visualise internal data flow bottlenecks that were eliminated by optimising test program code.