A scalable communication processor design supporting systolic communication
In getting a high performance computer we have the choice between expensive single processor systems and massive parallel computers. The latter are more difficult to program, but offer almost unlimited extensibility of computing power.
This paper describes a scalable and flexible communication processor for message passing in massive parallel processor systems. This communication processor is currently being implemented as a parameterized VLSI cell within a framework for automatic generation of application specific processors. It adds MIMD capabilities to this framework. In contrast to many existing designs, this design covers a large area within the communication processor design space.
Keywordshigh performance communication processor fine-grain communication virtual connections routing scalability of design message compression
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