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A unified software pipeline construction scheme for modulo scheduled loops

  • Instruction Level Parallelism
  • Conference paper
  • First Online:
Languages and Compilers for Parallel Computing (LCPC 1997)

Part of the book series: Lecture Notes in Computer Science ((LNCS,volume 1366))

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Abstract

We present a software pipeline construction scheme for DOloops, while-loops, and loops with multiple exits, which unifies, simplifies, and generalizes, the separate techniques previously required to build a complete software pipeline from a local schedule computed by modulo scheduling. In the setting of this software pipeline construction scheme, we demonstrate a simple way of implementing a general form of modulo expansion. Then we introduce inductive relaxation, a technique that replaces generalized modulo expansion when the variable to expand is a simple induction. These techniques do not require any architectural support from the target processor, and have been extensively tested as part of the software pipeliner that comes with the 3.0 compiler releases for the Cray T3ETM massively parallel computer.

On leave from the CEA CEL-V, 94195 Villeneuve St Georges cedex France. Part of this research was funded by the DGA grant ERE/SC N° 95-1137/A000/DRET/DS/SR.

Because “code generation” refers to another phase in the setting of our host compiler.

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References

  1. V. H. Allan, R. Jones, R. Lee, S. J. Allan “Software Pipelining” ACM Computing Surveys, Sep. 1995.

    Google Scholar 

  2. R. L. Sites “Alpha AXP Architecture” Digital Technical Journal, vol. 4, no. 2, 1992.

    Google Scholar 

  3. J. C. Dehnert, R. A. Towle “Compiling for Cydra 5” Journal of Supercomputing, vol. 7, pp. 181–227, May 1993.

    Google Scholar 

  4. B. Dupont de Dinechin “Insertion Scheduling: An Alternative to List Scheduling for Modulo Schedulers”, Proceedings of 8th international workshop on Language and Compilers for Parallel Computers, LNCS #1033, Columbus, Ohio, Aug. 1995.

    Google Scholar 

  5. B. Dupont de Dinechin “Efficient Computation of Margins and of Minimum Cumulative Register Lifetime Dates”, Proceedings of 9th International Workshop on Language and Compilers for Parallel Computers, San Jose, California, Aug. 1996.

    Google Scholar 

  6. M. Lam “A Systolic Array Optimizing Compiler” Ph. D. Thesis, Carnegie Mellon University, May 1987.

    Google Scholar 

  7. M. Lam “Software Pipelining: An Effective Scheduling Technique for VLIW Machines” Proceedings of the SIGPLAN'88 Conference on Programming Language Design and Implementation, 1988.

    Google Scholar 

  8. B. R. Rau, C. D. Glaeser “Some Scheduling Techniques and an Easily Schedulable Horizontal Architecture for High Performance Scientific Computing” IEEE / ACM 14th Annual Microprogramming Workshop, Oct. 1981.

    Google Scholar 

  9. B. R. Rau “Iterative Modulo Scheduling: An Algorithm for Software Pipelining Loops” IEEE / ACM 27th Annual Microprogramming Workshop, San Jose, California, Nov. 1994.

    Google Scholar 

  10. B. R. Rau, M. S. Schlansker, P. P. Tirumalai “Code Generation Schemas for Modulo Scheduled Loops” MICRO-25 / 25th Annual International Symposium on Microarchitecture, Portland, Dec. 1992.

    Google Scholar 

  11. J. Ruttenberg, G. R. Gao, A. Stoutchinin, W. Lichtenstein “Software Pipelining Showdown: Optimal vs. Heuristic Methods in a Production Compiler” Proceedings of the SIGPLAN'96 Conference on Programming Language Design and Implementation, Philadelphia, May 1996.

    Google Scholar 

  12. P. P. Tirumalai, M. S. Schlansker “Parallelization of Loops with Exits on Pipelined Architectures” Proceedings of the Supercomputing'90 conference Nov. 1990.

    Google Scholar 

  13. R. F. Touzeau “A Fortran Compiler for the FPS-164 Scientific Computer” ACM SIGPLAN 84 Symposium on Compiler Construction, 1984.

    Google Scholar 

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Authors and Affiliations

  1. ACAPS Laboratory, School of Computer Science, McGill University, USA

    Benoit Dupont de Dinechin

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  1. Benoit Dupont de Dinechin
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Editor information

Zhiyuan Li Pen-Chung Yew Siddharta Chatterjee Chua-Huang Huang P. Sadayappan David Sehr

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© 1998 Springer-Verlag Berlin Heidelberg

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de Dinechin, B.D. (1998). A unified software pipeline construction scheme for modulo scheduled loops. In: Li, Z., Yew, PC., Chatterjee, S., Huang, CH., Sadayappan, P., Sehr, D. (eds) Languages and Compilers for Parallel Computing. LCPC 1997. Lecture Notes in Computer Science, vol 1366. Springer, Berlin, Heidelberg. https://doi.org/10.1007/BFb0032706

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  • DOI: https://doi.org/10.1007/BFb0032706

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  • Publisher Name: Springer, Berlin, Heidelberg

  • Print ISBN: 978-3-540-64472-9

  • Online ISBN: 978-3-540-69788-6

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