A high performance SOFM hardware-system

  • S. Rüping
  • M. Porrmann
  • U. Rückert
Neural Nets Simulation, Emulation and Implementation
Part of the Lecture Notes in Computer Science book series (LNCS, volume 1240)


Many applications of Selforganizing Feature Maps (SOFMs) need a high performance hardware system in order to be efficient. Because of the regular and modular structure of SOFMs, a hardware realization is obvious. Based on the idea of a massively parallel system, several chips have been designed, manufactured and tested by the authors. In this paper a high performance system with the latest NBISOM_25 chips is presented. The NBISOM_25 integrated circuit contains 25 processing elements in a 5 by 5 array. Due to the scalability of the chips a VME-bus board was built with 16 ICs on it. The controller for the VME-bus and the SOFM hardware are realized using FPGAs. The system runs SOFM applications with up to 400 elements in parallel mode (20 by 20 map). Each weight vector can have up to 64 weights of 8 bit accuracy. The maximum performance of the board-system is 4.1 GCPS (recall) and 2.4 GCUPS (learning).


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Copyright information

© Springer-Verlag Berlin Heidelberg 1997

Authors and Affiliations

  • S. Rüping
    • 1
  • M. Porrmann
    • 1
  • U. Rückert
    • 1
  1. 1.Heinz Nixdorf InstituteUniversity of Paderborn, System and Circuit TechnologyPaderbornGermany

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