Abstract
Multiway Decision Graphs (MDGs) have recently been proposed as an efficient representation tool for RTL designs. In this paper we demonstrate the MDG-based formal verification technique on the example of the Island Tunnel Controller. We also provide comparative experimental results for the verification of a number of properties using two well-known ROBDD-based verification tools SMV (Symbolic Model verifier) and VIS (Verification Interacting with Synthesis). Finally, we study in detail the non-termination problem of the abstract state enumeration and present an solution.
This is a preview of subscription content, log in via an institution.
Preview
Unable to display preview. Download preview PDF.
References
R. E. Bryant. Graph-based algorithms for boolean function manipulation. IEEE Transactions on Computers, 35(8):677–691, August 1986.
R. E. Bryant and Y. Chen. Verification of arithmetic circuits with binary moment diagrams. In 32nd ACM/IEEE Design Automation Conference (DAC'95). San Francisco, California, June 1995.
R. K. Brayton et. al. VIS: A system for verification and synthesis. In Proc. 8th International Conference on Computer-Aided Verification (CAV'96). New Brunswick, New Jersey, USA, July 1996.
J. R. Burch, E. M. Clarke, D. E. Long, K. L. McMillan and D. L. Dill. Symbolic model checking for sequential circuit verification. IEEE Transactions on Computer-Aided Design, 13(4):401–424, April 1994.
J. R. Burch and D. L. Dill. Automatic verification of pipelined microprocessor control. In: D. L. Dill, editor, Computer Aided Verification. Lecture Notes in Computer Science 818, Springer Verlag, 1994.
E. M. Clarke, O. Grumberg, and D. E. Long. Model checking and abstraction. In Proc. 19th ACM Symp. on Principles of Programming Languages. January 1992.
E. Clarke, M. Fujita and X. Zhao. Hybrid decision diagrams. In Proc. IEEE Inter. Conf. on Computer-Aided Design (ICCAD'95). San Jose, California, USA, Nov. 1995.
F. Corella, Z. Zhou, X. Song, M. Langevin and E. Cerny. Multiway decision graphs for automated hardware verification. IBM technical report RC19676, July 1994. To appear in the journal Formal Methods in System Design.
F. Corella, M. Langevin, E. Cerny, Z. Zhou and X. Song. State enumeration with abstract descriptions of state machines. In Proc. IFIP WG 10.5 Advanced Research Working Conference on Correct Hardware Design and Verification Methods (Charme'95). Frankfurt, Germany, October 1995.
O. Coudert, C. Berthet and J. C. Madre. Verification of synchronous sequential machines based on symbolic execution. In J. Sifakis, editor, Automatic Verification Methods for Finite State Systems. Lecture Notes in Computer Science 407, Springer Verlag, 1989.
D. Cyrluk and P. Narendran. Ground Temporal Logic: A logic for hardware verification. In: D. L. Dill, editor, Computer Aided Verification. Lecture Notes in Computer Science 818, Springer Verlag, 1994.
K. Fisler and S. Johnson. Integrating design and verification environments through a logic supporting hardware diagrams. In Proc. IFIP Conference on Hardware Description Languages and their Applications (CHDL'95). Chiba, Japan, Aug. 1995.
R. B. Jones and D. L. Dill. Efficient validity checking for processor verification. In Proc. IEEE International Conference on Computer-Aided Design (ICCAD'95). San Jose, California, USA, November 1995.
D. E. Long. Model Checking, Abstraction, and Compositional Verification. PhD thesis, Carnegie Mellon University, 1993.
M. Langevin, S. Tahar, Z. Zhou, X. Song and E. Cerny. Behavioral Verification of an ATM switch fabric using implicit abstract state enumeration. In Proc. IEEE Inter. Conf. on Computer Design (ICCD'96). Austin, Texas, USA, Oct. 1996.
K. L. McMillan. Symbolic model checking. Kluwer Academic Publishers, Boston, Massachusetts, 1993.
S. Tahar, Z. Zhou, X. Song, E. Cerny and M. Langevin. Formal verification of an ATM switch fabric using multiway decision graphs. In Proc. IEEE Sixth Great Lakes Symposium on VLSI. Ames, Iowa, USA, March 1996.
K.D. Anon, N. Boulerice, E. Cerny, F. Corella, M. Langevin, X. Song, S. Tahar, Y. Xu, Z. Zhou. MDG tools for the verification of RTL designs. In Proc. 8th International Conference on Computer-Aided Verification (CAV'96). New Brunswick, New Jersey, USA, July 1996.
Z. Zhou, X. Song, S. Tahar, E. Cerny, F. Corella and M. Langevin. Formal verification of the Island Tunnel Controller using Multiway Decision Graphs. Technical Report 1042, D'IRO, Université de Montréal, Montréal, Canada, July 1996.
Author information
Authors and Affiliations
Editor information
Rights and permissions
Copyright information
© 1996 Springer-Verlag Berlin Heidelberg
About this paper
Cite this paper
Zhou, Z., Song, X., Tahar, S., Cerny, E., Corella, F., Langevin, M. (1996). Formal verification of the Island Tunnel Controller using Multiway Decision Graphs. In: Srivas, M., Camilleri, A. (eds) Formal Methods in Computer-Aided Design. FMCAD 1996. Lecture Notes in Computer Science, vol 1166. Springer, Berlin, Heidelberg. https://doi.org/10.1007/BFb0031811
Download citation
DOI: https://doi.org/10.1007/BFb0031811
Published:
Publisher Name: Springer, Berlin, Heidelberg
Print ISBN: 978-3-540-61937-6
Online ISBN: 978-3-540-49567-3
eBook Packages: Springer Book Archive