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Overcoming the limitations of the traditional loop parallelization

  • Ireneusz Karkowski
  • Henk Corporaal
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 1225)

Abstract

Previous research has shown existence of a huge potential of the coarse-grain parallelism in programs. This parallelism is however not always easy to exploit. Especially, when applying today's parallelizing compilers to typical applications from the “embedded” domain. This is mainly due to the deficiencies of the static data dependency analysis they relay on. This paper investigates the potentials of the loops parallelization techniques using dynamic loop analysis techniques. For a set of “embedded” benchmarks (including an MPEG-2 encoder) ∼4 times more loops could be parallelized, in comparison with a state-of-the-art compiler (SUIF [1]), leading to average speedups of 2.85 (on a 4 processor system). Dynamic analysis is however not “full-proof” — we intent to use it exclusively in cases when static analysis fails to give any answer, and only if the user asserts its applicability.

Keywords

multiprocessing loop parallelization techniques data dependency analysis high performance embedded system design 

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Copyright information

© Springer-Verlag Berlin Heidelberg 1997

Authors and Affiliations

  • Ireneusz Karkowski
    • 1
  • Henk Corporaal
    • 1
  1. 1.Delft University of Technologythe Netherlands

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