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A high-speed small RSA encryption LSI with low power dissipation

  • A. Satoh
  • Y. Kobayashi
  • H. Niijima
  • N. Ooba
  • S. Munetoh
  • S. Sone
Implementation(Hard/Soft)
Part of the Lecture Notes in Computer Science book series (LNCS, volume 1396)

Abstract

A 1024-bit RSA encryption LSI with DES and MD5 functions was developed. An RSA accelerator core implemented in the LSI is 4.9 MM2 in area, and has three 1024-bit adders that perform doubling, squaring, and exponential operations simultaneously. A 1024-bit RSA operation takes 23 msec with 100mA peak current at the maximum frequency of 45 MHz. A 1024-bit RSA key is generated in 0.3 sec by using arithmetic functions supported by the LSI. The throughputs of DES and MD5 at 45 MHz are 18.9 MB/sec and 29.7 MB/sec, respectively.

Keywords

Smart Card Modular Multiplication Modular Exponentiation Custom Macro Standard Digital Signal Processor 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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References

  1. [1]
    R. Rivest, A. Shamir and L. Adelman: “A Method for Obtaining Digital Signatures and Public-key Cryptosystems,” Comm. ACM, vol. 21, no. 2, pp. 120–126, 1978.Google Scholar
  2. [2]
    P. Montgomery: “Modular Multiplication without Trial Division,” Mathematics of Computation, vol. 44, no. 170, pp. 519–521, 1985.Google Scholar
  3. [3]
    P. Barret: “Implementing the Rivest Shamir and Adelman Public Key Encryption Algorithm on a Standard Digital Signal Processor,” Advances in Cryptology — Crypto '86, LNCS 263, Springer-Verlag, pp. 311–323, 1987.Google Scholar
  4. [4]
    H. Sedlak: “The RSA Cryptography Processor,” Advances in Cryptology — Eurocrypt'87, LNCS 293, Springer-Verlag, pp. 95–105, 1988.Google Scholar
  5. [5]
    D. de Waleffe and J-J.Quisquater: “CORSAIR: A Smart Card for Public Key Cryptosystems,” Advances in Cryptology — Crypto '90, LNCS 537, Springer-Verlag pp. 503–513, 1990.Google Scholar
  6. [6]
    D. Naccache and D. M'Raihi: “Cryptographic Smart Cards,” IEEE Micro, vol. 16, no. 3, pp. 14–24, June 1996.Google Scholar
  7. [7]
    P. A. Ivey, A. L. Cox, J. R. Harbridge and J. K. Oldfield: “A Single-Chip Public Key Encryption System,” IEEE J. Solid-State Circuits, vol. 24, no. 4, pp. 1071–1075, Aug. 1989.Google Scholar
  8. [8]
    M. Shand and J. Vuillemin: “Fast Implementations of RSA Cryptography,” Proceedings of the 11th IEEE Symp. on Computer Arithmetic, pp. 252–259, 1993.Google Scholar
  9. [9]
    P. A. Ivey, S. N. Walker, J. M. Stern and S. Davidson: “An Ultra-High Speed Public Key Encryption Processor,” Proceedings of IEEE 1992 Custom Integrated Circuits Conf. pp. 19.6.1-19.6.4, May 1992.Google Scholar
  10. [10]
    A. Vandemeulebroeck, E. Vanzieleghem, T. Denayer, and P. G. A. Jespers: “A New Carry-Free Division Algorithm and its Application to a Single-Chip 1024-b RSA Processor,” IEEE J. Solid-State Circuits, vol. 25, no. 3, pp. 748–756, June 1990.Google Scholar
  11. [11]
    FIPS PUB 46, “Data Encryption Standard,” National Bureau of Standards, 1977.Google Scholar
  12. [12]
    FIPS PUB 81, “DES Modes of Operation,” National Bureau of Standards, 1980.Google Scholar
  13. [13]
    R. Rivest: “The MD5 Message-Digest Algorithm,” RFC 1321, Apr. 1992.Google Scholar
  14. [14]
    http://www.pijnenburg.nl, Pijnenburg Beheer N.V.Google Scholar
  15. [15]
    http://www.nel.co.jp, NTT Electronics Co.Google Scholar
  16. [16]
    http://www.siemens.de, Siemens AG.Google Scholar
  17. [17]
    http://www.st.com, SGS-Thomson Microelectronics.Google Scholar
  18. [18]
    http://www.philps.com, Philips.Google Scholar
  19. [19]
    http://www.mcu.motsps.com, Motorola.Google Scholar
  20. [20]
    M. Lehman and N. Burla: “Skip Techniques for High-Speed Carry Propagation in Binary Arithmetic Units,” IRE Trans. Elec. Comput., vol. EC-10, pp. 691–698, Dec. 1961.Google Scholar
  21. [21]
    O. J. Bedrij: “Carry-Select Adder,” IRE Trans. Elec. Comput., vol. EC-11, pp. 340–346, June 1962.Google Scholar
  22. [22]
    C. Pomerance: “On the Distribution of Pseudoprimes,” Mathmatics of Computation, vol. 34, no. 156, pp. 587–593, Oct. 1981.Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 1998

Authors and Affiliations

  • A. Satoh
    • 1
  • Y. Kobayashi
    • 1
  • H. Niijima
    • 1
  • N. Ooba
    • 1
  • S. Munetoh
    • 1
  • S. Sone
    • 2
  1. 1.IBM research, Tokyo Research LaboratoryIBM Japan Ltd.,1623-14Yamato-shi, KanagawaJapan
  2. 2.IBM Microelectronics DivisionYasu Plant, IBM Japan Ltd.Yasu-gun, ShigaJapan

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