Real-time verification of Statemate designs
This paper presents a toolset for real-time verification of Statemate designs. Statemate is a widely used design tool for embedded control applications. In our approach designs including all timing information are translated into untimed finite state machines (FSMs) which are verified by symbolic model-checking. Real-time requirements are expressed by TCTL formulae interpreted over discrete time. A reduction from TCTL model-checking to CTL model-checking is implemented in order to use a CTL model-checker for the verification task. Some experimental results of the toolset are given.
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