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RESIS: A new methodology for register optimization in software pipelining

Workshop 20 Instruction Level Parallelism
Part of the Lecture Notes in Computer Science book series (LNCS, volume 1124)

Abstract

This paper presents a new technique to reduce the register pressure in pipelined schedules. A two-step approach is proposed: minimizing the SPAN of the loop and rearranging operations within a basic block. Experimental results show that further improvements on the schedules found by the best existing techniques can be obtained at the expense of a negligible computational cost.

Keywords

Critical Path Iteration Index Register Allocation Software Pipeline Final Schedule 
These keywords were added by machine and not by the authors. This process is experimental and the keywords may be updated as the learning algorithm improves.

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Copyright information

© Springer-Verlag Berlin Heidelberg 1996

Authors and Affiliations

  1. 1.Departament d'Arquitectura de ComputadorsUniversitat Politècnica de CatalunyaFrance

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