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IDRA (ideal resource allocation): Computing ideal speedups in parallel logic programming

  • M. J. Fernández
  • M. Carro
  • M. Hermenegildo
Workshop 19 Performance Evaluation
Part of the Lecture Notes in Computer Science book series (LNCS, volume 1124)

Abstract

We present a technique to estimate accurate speedups for parallel logic programs with relative independence from characteristics of a given implementation or underlying parallel hardware. The proposed technique is based on gathering accurate data describing one execution at run-time, which is fed to a simulator. Alternative schedulings are then simulated and estimates computed for the corresponding speedups. A tool implementing the aforementioned techniques is presented, and its predictions are compared to the performance of real systems, showing good correlation.

Keywords

Parallel Logic Programming Simulation Parallelism Concurrency Performance Evaluation 

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Copyright information

© Springer-Verlag Berlin Heidelberg 1996

Authors and Affiliations

  • M. J. Fernández
    • 1
  • M. Carro
    • 1
  • M. Hermenegildo
    • 1
  1. 1.School of Computer ScienceTechnical University of MadridSpain

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