A new concept for parallel neurocomputer architectures
This paper presents a new concept for a parallel neurocomputer architecture which is based on a configurable neuroprocessor design. The neuroprocessor adapts its internal parallelism dynamically to the required data precision for achieving an optimal utilization of the available hardware resources. This is realized by encoding a variable number of p different data elements in one very long data word of b bits. All components of the neuroproccessor (multiplier, accumulator, adder, ...) support the parallel execution of p operations on all data elements of one very long data word.
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