Design of the shared memory system for multi-processor lisp machines and its implementation on the evlis machine

  • Hiroshi Yasui
  • Toshikazu Sakaguchi
  • Kohichi Kudo
  • Nobuyuki Hironishi
Part II Parallel Lisp Systems and Architectures
Part of the Lecture Notes in Computer Science book series (LNCS, volume 441)


This paper presents the design and implementation of a shared memory system to reduce memory interference in an environment of a multi-processor system composed of a pool of EVAL-11 processors and aiming for high performance through parallel evaluation of a Lisp program.

The performance of a multi-processor system varies with many factors. We introduced several useful methods to control the granularity of the processes, and have confirmed their effect through dynamic measurement on the multi-processor Lisp machine — the EVLIS machine —. Dynamic measurement also shows that the interference of access to shared memory is a difficult problem. We show a solution for this problem in two different ways. First, we modified the form of the free cell list to reduce the interference from exclusive operation. Second, we present the design of the shared memory system which solves the memory interference on read accesses in particular, and its implementation with the use of conventional memory chips and TTL's.


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Copyright information

© Springer-Verlag Berlin Heidelberg 1990

Authors and Affiliations

  • Hiroshi Yasui
    • 1
  • Toshikazu Sakaguchi
    • 1
  • Kohichi Kudo
    • 1
  • Nobuyuki Hironishi
    • 1
  1. 1.Department of Applied Physics, Faculty of EngineeringOSAKA UniversityJapan

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