The use of model checking in ATPG for sequential circuits

  • P. Camurati
  • M. Gilli
  • P. Prinetto
  • M. Sonza Reorda
I. Tools And Computation
Part of the Lecture Notes in Computer Science book series (LNCS, volume 531)


Some design environments may prevent Design for Testability techniques from reducing testing to a combinational problem: ATPG for sequential devices remains a challenging field. Random and deterministic structure-oriented techniques are the state-of-the-art, but there is a growing interest in methods where the function implemented by the circuit is known. This paper shows how a test pattern may be generated while trying to disprove the equivalence of a good and a faulty machine. The algorithms are derived from Graph Theory and Model Checking. An example is analyzed to discuss the applicability and the cost of such an approach.


  1. [ACAg89]
    V.D. Agrawal, K.T. Cheng, P. Agrawal: “A directed search method for test generation using a concurrent fault simulator,” IEEE Transactions on Computer-Aided Design, Vol. 8, n. 2, February 1989, pp. 131–138Google Scholar
  2. [BBKo89]
    F. Brglez, D. Bryan, K. Koźminiński: “Combinational profiles of sequential benchmark circuits,” ISCAS'89: IEEE International Symposium on Circuits And Systems, Portland, OR (USA), May 1989, pp. 1929–1934Google Scholar
  3. [BCDM86]
    M. Browne, E.M. Clarke, D. Dill, B. Mishra: “Automatic verification of sequential circuits using temporal logic,” IEEE Transactions on Computers, Vol. C-35, n. 12, December 1986, pp. 1035–1044Google Scholar
  4. [BEGP86]
    F.P.M. Beenker, K.J.E. van Erdewijk, R.B.W. Geritzen, F.F. Peacock, M. van der Star: “Macro Testing: Unifying IC and Board Test,” IEEE Design & Test of Computers, December 1986, pp. 26–32Google Scholar
  5. [CESi86]
    E.M. Clarke, E.A. Emerson, A.P. Sistla: “Automatic verification of finitestate concurrent systems using temporal logic specifications,” ACM Transactions on Programming Languages and Systems, Vol. 8, n. 2, April 1986, pp. 244–263Google Scholar
  6. [CGSR89]
    G. Cabodi, S. Gai, M. Sonza Reorda: “Partitioning Techniques in Multiprocessor Simulators,” ESM-89: European Simulation Multiconference, Rome (Italy), June 1989, pp. 311–317Google Scholar
  7. [Chen88]
    W.T. Cheng: “The Back Algorithm for sequential test generation,” ICCD'88: IEEE International Conference on Computer Design, Rye Brook, NY (USA), October 1988, pp. 66–69Google Scholar
  8. [ChJo90]
    K-T. Cheng, J-Y. Jou: “Functional test generation for Finite State Machines,” ITC'90: International Test Conference 1990, Washington, DC (USA), September 1990, pp. 162–168Google Scholar
  9. [Fuji85]
    H. Fujiwara: “Logic testing and design for testability,” The MIT Press, Cambridge, MA (USA), 1975Google Scholar
  10. [HuSe89]
    R.V. Hudli, S.C. Seth: “Temporal Logic based test generation for sequential circuits,” IFIP TC 10/WG 10.2 Working Conference on CAD systems using AI techniques, Tokyo (Japan), June 1989, pp. 91–98Google Scholar
  11. [Koha70]
    Z. Kohavi: “Switching and finite automata theory,” Computer Science Series, Mc Graw Hill, New York, NY (USA), 1970Google Scholar
  12. [Marl86]
    R. Marlett: “An effective test generation system for sequential circuits,” DAC-23: 23th IEEE/ACM Design Automation Conference, Las Vegas, NV (USA), June 1986, pp. 250–256Google Scholar
  13. [McCl86]
    E.J. McCluskey: “Logic Design Principles with Emphasis on Testable Semicustom Circuits,” Prentice-Hall, Englewood Cliffs, NJ (USA), 1986Google Scholar
  14. [MDNS88]
    H.K.T. Ma, S. Devadas, A.R. Newton, A. Sangiovanni-Vincentelli: “Test generation for sequential circuits,” IEEE Transactions on Computer-Aided Design, Vol. 7, n. 10, October 1988, pp. 1081–1093Google Scholar
  15. [Moto90]
    A. Motohara: “Design for Testability of ASICs in Japan,” IEEE 13th Annual Workshop on Design for Testability, Vail, CO (USA), April 1990, (Oral presentation; no proceedings available) Google Scholar
  16. [Muth76]
    P. Muth: “A nine-valued circuits model for test generation,” IEEE Transactions on Computers, Vol. C-25, n. 6, June 1976, pp. 630–636Google Scholar
  17. [PoMC64]
    J.F. Poage, E.J. McCluskey: “Derivation of optimum test sequences for sequential machines,” 5th Annual Symposium on Switching Theory and Logical Design, 1964Google Scholar
  18. [PuRo71]
    G.R. Putzolu, J.P. Roth: “A heuristic algorithm for the testing of asynchronous circuits,” IEEE Transactions on Computers, Vol. C-20, n. 6, June 1971, pp. 639–647Google Scholar
  19. [ReUr71]
    N. Rescher, A. Urquart: “Temporal Logic,” Springer-Verlag Library of Exact Philosophy N. 3, Springer-Verlag, Berlin (FRG), 1971Google Scholar
  20. [ScAu89]
    M.H. Schulz, E. Auth: “ESSENTIAL: an efficient self-learning test pattern generation algorithm for sequential circuits,” ITC'89: International Test Conference 1989, Washington, DC (USA), September 1989, pp. 28–37Google Scholar
  21. [ShMC76]
    J.J. Shedletsky, E.J. McCluskey: “The error latency of a fault in a sequential digital circuit,” IEEE Transactions on Computers, Vol. C-25, n. 6, June 1976, pp. 655–659Google Scholar
  22. [WiPa82]
    T.W. Williams, K.P. Parker: “Design for Testability — a survey,” IEEE Transactions on Computers, Vol. C-31, n. 1, January 1982, pp. 2–15Google Scholar
  23. [Wolf90]
    W. Wolf: “The FSM network model for behavioral synthesis of controldominated machines,” DAC-27: 27th IEEE/ACM Design Automation Conference, Orlando, FL (USA), June 1990Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 1991

Authors and Affiliations

  • P. Camurati
    • 1
  • M. Gilli
    • 1
  • P. Prinetto
    • 1
  • M. Sonza Reorda
    • 1
  1. 1.Dipartimento di Automatica e InformaticaPolitecnico di TorinoTurinItaly

Personalised recommendations