Correct compilation of specifications to deterministic asynchronous circuits

  • Scott F. Smith
  • Amy E. Zwarico
Conference paper
Part of the Lecture Notes in Computer Science book series (LNCS, volume 683)


We have shown that Martin et al.'s methodology can be made more rigorous. In order to accomplish this the new concepts of partial declarations, module and component, mutual exclusion violations, fairness, handshaking variables, distinguished ports, equational rewriting, separate compilation and observable determinism were introduced.

Two recent papers address the same general problem of proving correctness of asynchronous circuit compilation [WBB92, vB92]. These two systems are more closely related to each other than either are to our work. In brief, the main advantage over our work is lack of the mutual exclusion issue and complications introduced thereby, and the disadvantages are expressiveness of the specification language and speed of resulting circuits.

In a prelimary report [WBB92], Weber, Bloom, and Brown define a process language Joy and its compilation to asynchronous circuitry. Joy has a number of syntactic restrictions including the restriction that no processes may share variables or passive port names. Their correctness proof is based on a bisimulation equivalence, which does not incorporate fairness.

van Berkel gives a correctness proof for compiling the CSP-based specification language Tangram to circuits. Tangram can only have single uses of each port, and disallows concurrent reads. His proof of correctness is based on a trace equivalence that does not take fairness into account.


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Copyright information

© Springer-Verlag Berlin Heidelberg 1993

Authors and Affiliations

  • Scott F. Smith
    • 1
  • Amy E. Zwarico
    • 1
  1. 1.Department of Computer ScienceThe Johns Hopkins UniversityBaltimoreUSA

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