Balanced systems: A new approach to integrate hardware and software design
The runtime gain to be obtained by integrating hardware and software design is substantial. E.g. in memory hierarchies, in particular in caches, performance increases of typically 20% could be observed for a wide selection of workloads. These performance increases have been acquired in a first step without using knowledge about program behavior. Higher benefits can be expected for a specifically designed algorithm.
In the project “Balanced Systems” a prototype is developed which uses knowledge about program behavior. Based upon reorganization of code and data a tool will be implemented providing a cache optimized link order of the program modules. Extending this tool to the optimization of procedures will lead to further performance increases due to finer granularity of the reorganized units. This adaption can be done without changing the reorganization algorithm. Only a new backend controlling procedures instead of link modules has to be implemented.
The prototype is based on a standard file format. Therefore it is portable to different UNIX systems. The optimization strategy is independent of the underlying computer architecture and can be successfully applied to all cache oriented RISC and CISC systems.
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- [HENN84]Hennessy, J.L.: VLSI Processor Architecture, IEEE Transactions on Computers, Vol. C-33, Dez. 1984, pp. 1221–1246Google Scholar
- [HENN90]Hennessy, J. L.; Patterson, D. A.: Computer Architecture: A Quantitative Approach, Morgan Kaufmann, San Mateo, CA, 1990Google Scholar
- [MCFA89]McFarling, S.: Program optimization for instruction caches, Proc. Third International Conf. on Architectural Support for Programming Languages and Operating Systems, April 1989, Boston, Mass., pp. 183–191Google Scholar
- [MIPS89]MIPS RISComputer System Programmer's Package Reference, March 1989Google Scholar
- [PATT85]Patterson, D.A.: Reduced Instruction Set Computers, Communications of the ACM 28(1), Jan. 1985, pp. 8–21Google Scholar
- [SMIT82]Smith, A. J.: Cache memories, Computing Surveys 14:3, September 1982, pp. 473–530Google Scholar
- [SPEC90]SPEC Benchmark Suite Release 1.2b, December 1990, SPEC c/o NCGA, 2722 Merrilee Drive, Suite 200, Fairfax, VA 22301, USA.Google Scholar