Atomic multireader register
We give implementations for atomic, shared, asynchronous, wait-free registers: (i) A new implemenfation of an atomic, 1-writer, 1-reader, b-bit register from O (b) safe, boolean registers (i.e., from scratch). The solution uses neither repeated writing of the input nor repeated reading of the output. (ii) An implementation of an atomic, 1-writer, n-reader, multibit register from O(n2) atomic, 1-writer, 1-reader, multibit registers. Both constructions rely on the same idea. In a sense (ii) is a generalization of (i). These results show how to construct atomic, multireader registers from — basically — elementary hardware like flip-flops.
1980 Mathematics Subject Classification (1985 Revision)Primary: 68M10 Secondary: 68P15. 68Q25
CR Classification System (1987 Version)B.3.2 B.4.3. D.4.1. D.4.2 D.4.4
Keywords and PhrasesRegister shared register atomic regular reader writer
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