Advertisement

Automatic test pattern generation on multiprocessors: a summary of results

  • Sunil Arvindam
  • Vipin Kumar
  • V. Nageshwara Rao
  • Vineet Singh
Computer Architecture And Parallel Processing
Part of the Lecture Notes in Computer Science book series (LNCS, volume 444)

Abstract

Test generation of combinational circuits is an important step in the VLSI design process. Unfortunately, the problem is highly computation-intensive and, for circuits encountered in practice, test generation time can often be enormous. In this paper, we present a parallel formulation of a backtrack search algorithm called PODEM, which has been the most successful algorithm for this problem. The sequential PODEM algorithm consumes most of its execution time in generating a test for “hard-to-detect” (HTD) faults and is often unable to detect them even after a large number of bactracks. Our parallel formulation attempts to overcome these limitations by partitioning the search space in order to search it concurrently using multiple processors.

We present speedup results and performance analyses of our formulation on a 128 processor Symult s2010 multicomputer. Our results show that parallel search techniques provide good speedups (45–106 on 128 processors) as well as high fault coverage of the HTD faults in reasonable time as compared to the uniprocessor implementation.

Tree search is an integral part of several AI systems. Effective parallel processing of search problems is important in developing high performance knowledge-based systems. Results from this paper show that tree search can be effectively parallelized on large scale parallel processors in the context of practical problems.

Preview

Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.

References

  1. [Arvindam et al. 1989]
    S. Arvindam, V. Kumar, V.N. Rao and V. Singh. Automatic Test Pattern Generation on Multiprocessors. MCC Tech Report ACT-OODS-240-89, 1989.Google Scholar
  2. [Bennetts 1984]
    R.G. Bennetts. Design of Testable Logic Circuits. Addison-Wesley, Reading, Massachusetts, 1984.Google Scholar
  3. [Brglez and Fujiwara 1985]
    F. Brglez and H. Fujiwara. Neutral Netlist of Ten Combinational Benchmark Circuits and a Target Translator in Fortran. In Special Session on ATPG and Fault Simulation, Proceedings of IEEE International Symposium on Circuits and Systems, July 1985.Google Scholar
  4. [Goel 1980]
    P. Goel. Test Generation Cost Analysis and Projections. In Proceedings, 17th Design Automation Conference, June 1980.Google Scholar
  5. [Goel 1981]
    P. Goel. An Implicit Enumeration Algorithm to Generate Tests for Combinational Logic Circuits. IEEE Trans. on Computers, C-30:215–222, March 1981.Google Scholar
  6. [Kumar and Rao 1988]
    V. Kumar and V. N. Rao. Parallel Depth-First Search, Part II: Analysis. International Journal of Parallel Programming, 16 (6):501–519, 1987.Google Scholar
  7. [Kumar and Rao 1989]
    V. Kumar and V. N. Rao. Load balancing on the Hypercube Architecture. In Proceedings, Fourth Conf. on Hypercubes, Concurrent Computers and Applications, March 1989.Google Scholar
  8. [Kumar et al. 1989]
    V. Kumar et al.. Working Manuscript.Google Scholar
  9. [Motohara et al. 1986]
    A. Motohara, K. Nishimura, H. Fujiwara and I. Shirakawa. A Parallel Scheme for Test Pattern Generation. In Proceedings, Intl. Conference on Computer-Aided Design, 1986, pages 156–159.Google Scholar
  10. [Patil and Banerjee 1989]
    S. Patil and P. Banerjee. A Parallel Branch-and-Bound Algorithm for Test Generation. Proceedings of the 26th ACM/IEEE Design Automation Conference, 1989.Google Scholar
  11. [Rao and Kumar 1988]
    V.N. Rao and V. Kumar. Parallel Depth-First Search, Part I: Implementation. International Journal of Parallel Programming, 16 (6):479–499, 1987.Google Scholar
  12. [Rao and Kumar 1988]
    V.N. Rao and V. Kumar. Superlinear Speedup in State-Space Search. In Proceedings, Conference on Foundations of Software Technology and Theoretical Computer Science, December 1988.Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 1990

Authors and Affiliations

  • Sunil Arvindam
    • 3
  • Vipin Kumar
    • 2
  • V. Nageshwara Rao
    • 1
  • Vineet Singh
    • 3
  1. 1.Department of Computer SciencesUniversity of Texas at AustinAustin
  2. 2.Computer Science DepartmentUniversity of MinnesotaMinneapolis
  3. 3.MCCAustin

Personalised recommendations