Memory optimizations in the Intel Reference Compiler

  • K. Sridharan
  • Pohua Chang
  • Utpal Banerjee
  • Ravi Narayanaswamy
  • Suresh Rao
Poster Session Papers
Part of the Lecture Notes in Computer Science book series (LNCS, volume 1239)


Unable to display preview. Download preview PDF.

Unable to display preview. Download preview PDF.


  1. [1]
    Intel Corporation, “Intel Reference FORTRAN Compiler User's Guide for UNIX Systems,” Order number 484344-002.Google Scholar
  2. [2]
    David Callahan, Steve Carr, and Ken Kennedy, “Improving register allocation for subscripted variables,” Proceedings of the ACM SIGPLAN Symposium on Programming Language Design and Implementation, 1990.Google Scholar
  3. [3]
    Allan Porterfield, “Compiler management of program locality,” Rice COMP TR-88-63, January 1988.Google Scholar
  4. [4]
    Michael E. Wolf and Monica S. Lam, “A data locality optimizing algorithm,” Proceedings of the ACM SIGPLAN Symposium on Programming Language Design and Implementation, 1991.Google Scholar
  5. [5]
    Alvin R. Lebeck and David A. Wood, “Cache profiling and the SPEC benchmark: a case study,” Technical report, University of Wisconsin, March 1992.Google Scholar
  6. [6]
    F. E. Allen and J. Cocke, “A catalogue of optimizing transformations,” in Design and Optimization of Compilers, Prentice-Hall, 1972.Google Scholar
  7. [7]
    A. Aiken and A. Nicolau, “Loop quantization: an analysis and algorithm,” Technical report 87-821, Cornell U., March 1987.Google Scholar
  8. [8]
    D. Callahan, J. Cocke, and K. Kennedy, “Estimating interlock and improving balance for pipelined machines,” Journal of Parallel and Distributed Computing, 5, 1988.Google Scholar
  9. [9]
    M. Wolfe, “Advanced loop interchange,” Proceedings of the 1986 International Conference on Parallel Processing, August 1986.Google Scholar
  10. [10]
    J. R. Allen and K. Kennedy, “Automatic translation of Fortran programs to vector form,” ACM Transactions on Programming Languages and Systems, 9(4), October 1987.Google Scholar
  11. [11]
    M. Wolfe, “Iteration space tiling for memory hierarchies,” Proceedings of the Third SIAM Conference on Parallel Processing for Scientific Computing, December 1987.Google Scholar
  12. [12]
    A. K. Porterfield, “Software methods for improvement of cache performance on supercomputer applications,” Ph.D. thesis, Rice U., May 1989.Google Scholar
  13. [13]
    J. Ferrante, V. Sarkar, and W. Thrash, “On estimating and enhancing cache effectiveness,” in Fourth Workshop on Languages and Compilers for Parallel Computing, August 1991.Google Scholar
  14. [14]
    D. Gannon, W. Jalby, and K. Gallivan, “Strategies for cache and local memory management by global program transformations,” Proceedings of the First ACM International Conference on Supercomputing, June 1987.Google Scholar
  15. [15]
    U. Banerjee, Dependence Analysis for Supercomputing, Kluwer Academic Publishers, 1988.Google Scholar
  16. [16]
    U. Banerjee, Loop Transformations for Restructuring Compilers: The Foundations, Kluwer Academic Publishers, 1993.Google Scholar
  17. [17]
    U. Banerjee, Loop Transformations for Restructuring Compilers: Loop Parallelization, Kluwer Academic Publishers, 1994.Google Scholar
  18. [18]
    M. Wolfe, Optimizing Supercompilers for Supercomputers, MIT Press, 1989.Google Scholar

Copyright information

© Springer-Verlag Berlin Heidelberg 1997

Authors and Affiliations

  • K. Sridharan
    • 1
  • Pohua Chang
    • 1
  • Utpal Banerjee
    • 1
  • Ravi Narayanaswamy
    • 1
  • Suresh Rao
    • 1
  1. 1.Intel Architecture Lab M/S RN6-18Santa Clara

Personalised recommendations