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An interprocedural parallelizing compiler and its support for memory hierarchy research

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Languages and Compilers for Parallel Computing (LCPC 1995)

Part of the book series: Lecture Notes in Computer Science ((LNCS,volume 1033))

Abstract

We present several new compiler techniques employed by our interprocedural parallelizing research compiler, Panorama, to improve loop parallelization and the efficiency of memory references. We first present an overview of the compiler and its associated memory architecture simulation environments. We then present an interprocedural array dataflow analysis, using guarded array regions, for automatic array privatization, an interprocedural static profile analysis, and a graph reduction algorithm for parallel task assignment and data allocation which aims at reducing remote memory references while maintaining loop parallelism.

Sponsored in part by U.S. Army, Army Research Laboratory, Army HPC Research Center. No official endorsement should be inferred. This work is also supported in part by National Science Foundation, grant CCR-9210913, and by Computing Devices, International.

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Chua-Huang Huang Ponnuswamy Sadayappan Utpal Banerjee David Gelernter Alex Nicolau David Padua

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© 1996 Springer-Verlag Berlin Heidelberg

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Nguyen, T., Gu, J., Li, Z. (1996). An interprocedural parallelizing compiler and its support for memory hierarchy research. In: Huang, CH., Sadayappan, P., Banerjee, U., Gelernter, D., Nicolau, A., Padua, D. (eds) Languages and Compilers for Parallel Computing. LCPC 1995. Lecture Notes in Computer Science, vol 1033. Springer, Berlin, Heidelberg. https://doi.org/10.1007/BFb0014194

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  • DOI: https://doi.org/10.1007/BFb0014194

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  • Online ISBN: 978-3-540-49446-1

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