Scheduling instructions with uncertain latencies in asynchronous architectures
This paper addresses the problem of scheduling instructions in micronet-based asynchronous processors (MAP), in which the latencies of the instructions are not precisely known. A PTD scheduler is proposed which minimises true dependencies, and results are compared with two list schedulers — the Gibbons and Muchnick scheduler, and a variation of the Balanced scheduler. The PTD scheduler has a lower time complexity and produces better quality schedules than the other two when applied twenty-three loop- and control-intensive benchmark programs.
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- 1.D. K. Arvind and V. E. F. Rebello. Instruction-level parallelism in asynchronous processor architectures. Proc 3rd. International Workshop on Algorithms and Parallel VLSI Leuven, Belgium, August 1994, pp. 203–215.Google Scholar
- 2.P. B. Gibbons and S. S. Muchnick. Efficient instruction scheduling for a pipelined architecture. Proc. SIGPLAN 1986 Symposium on Compiler Construction, SIGPLAN Notices, 21(7), July 1986, pp. 11–16.Google Scholar
- 3.D. R. Kerns and S. J. Eggers. Balanced scheduling: Instruction scheduling when memory latency is uncertain. In Proc SIGPLAN 1993 Conference on Programming Language Design and Implementation, SIGPLAN Notices, 28(6), June 1993, pp. 278–289.Google Scholar
- 4.D. J. Kinniment. An evaluation of asynchronous addition. IEEE Transactions on Very Large Scale Integration (VLSI) systems, March 1996, pp. 137–140.Google Scholar