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Scheduling instructions with uncertain latencies in asynchronous architectures

  • D. K. Arvind
  • S. Sotelo-Salazar
Workshops 10+11+14: Parallel Computer Architecture and Image Processing
Part of the Lecture Notes in Computer Science book series (LNCS, volume 1300)

Abstract

This paper addresses the problem of scheduling instructions in micronet-based asynchronous processors (MAP), in which the latencies of the instructions are not precisely known. A PTD scheduler is proposed which minimises true dependencies, and results are compared with two list schedulers — the Gibbons and Muchnick scheduler, and a variation of the Balanced scheduler. The PTD scheduler has a lower time complexity and produces better quality schedules than the other two when applied twenty-three loop- and control-intensive benchmark programs.

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References

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    P. B. Gibbons and S. S. Muchnick. Efficient instruction scheduling for a pipelined architecture. Proc. SIGPLAN 1986 Symposium on Compiler Construction, SIGPLAN Notices, 21(7), July 1986, pp. 11–16.Google Scholar
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    D. R. Kerns and S. J. Eggers. Balanced scheduling: Instruction scheduling when memory latency is uncertain. In Proc SIGPLAN 1993 Conference on Programming Language Design and Implementation, SIGPLAN Notices, 28(6), June 1993, pp. 278–289.Google Scholar
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Copyright information

© Springer-Verlag Berlin Heidelberg 1997

Authors and Affiliations

  • D. K. Arvind
    • 1
  • S. Sotelo-Salazar
    • 1
  1. 1.Department of Computer ScienceThe University of EdinburghEdinburghScotland

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