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A Low-Power Analog Bell-Shaped Classifier Based on Parallel-Connected Gaussian Function Circuits

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Frontiers of Artificial Intelligence, Ethics, and Multidisciplinary Applications (FAIEMA 2023)

Abstract

In this study, a novel approach is presented for developing ultra-low power analog classifiers capable of effectively handling multiple input features while maintaining high levels of accuracy and minimizing power consumption. The proposed methodology is built upon a Voting model that leverages Gaussian likelihood functions. To evaluate the performance of the proposed methodology, a comparison is conducted against the widely used analog Bell-shaped classifiers. Real-life breast cancer dataset is employed for this comparison. The models are trained and the results are processed using the Python programming language. The hardware design and result processing utilize Cadence IC Suite, implementing the TSMC 90 nm CMOS process technology.

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References

  • Alimisis V, Gennis G, Dimas C, Sotiriadis PP (2021) An analog Bayesian classifier implementation, for thyroid disease detection, based on a low power, current-mode gaussian function circuit. In: 2021 International conference on microelectronics (ICM), pp 153–156

    Google Scholar 

  • Alimisis V, Gennis G, Tsouvalas E, Dimas C, Sotiriadis PP (2022) An analog, low-power threshold classifier tested on a bank note authentication dataset. In: 2022 International conference on microelectronics (ICM), pp 66–69

    Google Scholar 

  • Alimisis V et al (2022) Gaussian Mixture Model classifier analog integrated low power implementation with applications in fault management detection. Microelectron J 126:105510

    Article  Google Scholar 

  • Alimisis V et al (2022) A hand gesture recognition circuit utilizing an analog voting classifier. Electronics 11:3915

    Article  Google Scholar 

  • Alimisis V, Gourdouparis M, Gennis G, Dimas C, Sotiriadis PP (2021) Analog gaussian function circuit: architectures, operating principles and applications. Electronics 10:2530

    Article  Google Scholar 

  • Alimisis V, Gennis G, Gourdouparis M, Dimas C, Sotiriadis PP (2023) A low-power analog integrated implementation of the support vector machine algorithm with on-chip learning tested on a bearing fault application. Sensors 23:3978

    Article  Google Scholar 

  • Aslanpour MS et al (2021) Serverless edge computing: vision and challenges. In: Proceedings of the 2021 Australasian computer science week multiconference, pp 1–10

    Google Scholar 

  • Bahai A (2016) Ultra-low energy systems: analog to information. In: ESSCIRC conference 2016: 42nd European solid-state circuits conference, pp 3–6

    Google Scholar 

  • Bishop CM, Nasrabadi NM (2006) Pattern recognition and machine learning. Springer, p 4

    Google Scholar 

  • Bouguila N, Fan W (2020) Mixture models and applications. Springer

    Google Scholar 

  • Delbrueck T, Mead C (1993) Bump circuits. In: Proceedings of International joint conference on neural networks, vol 1, pp 475–479

    Google Scholar 

  • Ding C et al (2018) Structured weight matrices-based hardware accelerators in deep neural networks: Fpgas and asics. In: Proceedings of the 2018 on great lakes symposium on VLSI, pp 353–358

    Google Scholar 

  • Georgakilas E et al (2023) An ultra-low power fully-programmable analog general purpose type-2 fuzzy inference system. AEU-Int J Electr Commun:154824

    Google Scholar 

  • Geweke J, Amisano G (2011) Hierarchical Markov normal mixture models with applications to financial asset returns. J Appl Economet 26:1–29

    Article  Google Scholar 

  • Haensch W, Gokmen T, Puri R (2018) The next generation of deep learning hardware: analog computing. Proc IEEE 107:108–122

    Article  Google Scholar 

  • Haidar A, Dong T, Luszczek P, Tomov S, Dongarra J (2015) Batched matrix computations on hardware accelerators based on GPUs. Int J High Perform Comput Appl 29:193–208

    Article  Google Scholar 

  • Hock M, Hartel A, Schemmel J, Meier K (2013) An analog dynamic memory array for neuromorphic hardware. In: 2013 European conference on circuit theory and design (ECCTD), pp 1–4

    Google Scholar 

  • Hussain F, Hussain R, Hassan SA, Hossain E (2020) Machine learning in IoT security: current solutions and future challenges. IEEE Commun Surv Tutor 22:1686–1721

    Article  Google Scholar 

  • Khan MA et al (2022) Voting classifier-based intrusion detection for iot networks. In: Advances on smart and soft computing: proceedings of ICACIn 2021, pp 313–328

    Google Scholar 

  • Lazzaro J, Ryckebusch S, Mahowald MA, Mead CA (1988) Winner-take-all networks of O (n) complexity. Adv Neural Inf Process Syst 1

    Google Scholar 

  • Lee KJ, Lee J, Choi S, Yoo H-J (2020) The development of silicon for AI: different design approaches. IEEE Trans Circuits Syst I Regul Pap 67:4719–4732

    Article  Google Scholar 

  • Mangasarian OL, Wolberg WH (1990) Cancer diagnosis via linear programming, technical report. University of Wisconsin-Madison Department of Computer Sciences

    Google Scholar 

  • Panic B, Klemenc J, Nagode M (2020) Gaussian mixture model based classification revisited: application to the bearing fault classification. J Mech Eng/Strojniški Vestnik 66

    Google Scholar 

  • Strubell E, Ganesh A, McCallum A (2019) Energy and policy considerations for deep learning in NLP. Preprint at arXiv:1906.02243

  • Wang A, Calhoun BH, Chandrakasan AP (2006) Sub-threshold design for ultra low-power systems. Springer

    Google Scholar 

  • Weber R, Gothandaraman A, Hinde RJ, Peterson GD (2010) Comparing hardware accelerators in scientific applications: a case study. IEEE Trans Parallel Distrib Syst 22:58–68

    Article  Google Scholar 

  • Zhang X et al (2018) DNNBuilder: an automated tool for building high-performance DNN hardware accelerators for FPGAs. In: 2018 IEEE/ACM international conference on computer-aided design (ICCAD), pp 1–8

    Google Scholar 

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Correspondence to Vassilis Alimisis .

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Alimisis, V., Kamperi, A., Eleftheriou, N.P., Sotiriadis, P.P. (2024). A Low-Power Analog Bell-Shaped Classifier Based on Parallel-Connected Gaussian Function Circuits. In: Farmanbar, M., Tzamtzi, M., Verma, A.K., Chakravorty, A. (eds) Frontiers of Artificial Intelligence, Ethics, and Multidisciplinary Applications. FAIEMA 2023. Frontiers of Artificial Intelligence, Ethics and Multidisciplinary Applications. Springer, Singapore. https://doi.org/10.1007/978-981-99-9836-4_34

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