Abstract
The chapter examines the latest advancements in electronic interconnect technologies and their effects on system design. It discusses the increasing need for advanced interconnect technologies in catering to faster data transfer, advanced image processing, and stronger computing power, emphasizing the significance of integrating various components into one device. The chapter also analyzes current trends in chip-packages, circuit boards, cables, and connectors, and their contribution to the electronic industry's growth. A brief overview on the trends in the technologies pertaining to high-speed serializer/deserializer, memory and printed/flexible electronics is presented. The chapter offers a comprehensive overview of the most significant trends and advancements in high-speed electronics, making it an indispensable resource for designers and engineers in the field.
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References
Acito B (2019) Leveraging the best of package and IC design for system enablement. In: 2019 international wafer level packaging conference (IWLPC). IEEE, San Jose, CA, USA, pp 1–4. https://doi.org/10.23919/IWLPC.2019.8914109
AMD EPYC™ 9004 series processors. https://www.amd.com/en/partner/4th-generation-amd-epyc
Addressing memory performance for 100G ethernet networking. https://www.chipestimate.com/Addressing-Memory-Performance-for-100G-Ethernet-Networking/Memoir-Systems/Technical-Article/2012/09/18
Ansys electronics-electromagnetic, signal integrity, thermal and electro-mechanical simulation solutions. https://www.ansys.com/en-in/products/electronics
Chen S, Li C, Chen Y, Zhang W, Zhong J, Cai J (2015) Study on electrical performance of stacking die package with silicon interposer. In: 2015 16th international conference on electronic packaging technology (ICEPT). IEEE, Changsha, China, pp 1158–1161. https://doi.org/10.1109/ICEPT.2015.7236785
Chunquan L, Xiaole K (2010) Effects of ground vias on high-speed signal transmission in high-speed PCB design. In: 2010 11th international conference on electronic packaging technology & high density packaging. IEEE, Xi’an, China, pp 88–91. https://doi.org/10.1109/ICEPT.2010.5582357
Choosing between DDR4 and HBM in memory-intensive applications. https://www.techdesignforums.com/practice/technique/choosing-between-ddr4-and-hbm-in-memory-intensive-applications
Duan G, Kanaoka Y, McRee R, Nie B, Manepalli R (2021) Die embedding challenges for EMIB advanced packaging technology. In: 2021 IEEE 71st electronic components and technology conference (ECTC). IEEE, San Diego, CA, USA, pp 1–7. https://doi.org/10.1109/ECTC32696.2021.00012
Die stacking and the system(2012) In: 2012 IEEE hot chips 24 symposium (HCS). IEEE, Cupertino, CA, USA, pp 1–18. https://doi.org/10.1109/HOTCHIPS.2012.7476475
Dsilva H, McMorrow S, Gregory A, Krooswyk S, Mellitz R, Lee B (2021) De-mystifying the impact of Intra-pair Skew on high-speed SerDes Interconnect. In: 2021 IEEE 25th workshop on signal and power integrity (SPI). IEEE, Siegen, Germany, pp 1–4. https://doi.org/10.1109/SPI52361.2021.9505171
Electronic skin patches 2021–2031. https://www.idtechex.com/en/research-report/electronic-skin-patches-2021-2031/821#:~:text=It%20reveals%20significant%20opportunity%2C%20with,products%20attached%20to%20the%20skin
Engin AE, Ndip I, Lang K-D, Aguirre J (2019) Closed-form multipole debye model for time-domain modeling of lossy dielectrics. IEEE Trans Electromagn Compat 61:966–968. https://doi.org/10.1109/TEMC.2018.2838522
Gao H, De S, Payne S (2020a) Impact of surface roughness on return planes in high speed signal propagation. In: 2020a IEEE international symposium on electromagnetic compatibility & signal/power integrity (EMCSI). IEEE, Reno, NV, USA, pp 150–154. https://doi.org/10.1109/EMCSI38923.2020.9191511
Gao G, Theil J, Fountain G, Workman T, Guevara G, Uzoh C, Suwito D, Lee B, Bang KM, Katkar R, Mirkarimi L (2020b) Die to wafer hybrid bonding: multi-die stacking with Tsv integration. In: 2020b international wafer level packaging conference (IWLPC). IEEE, San Jose, CA, USA, pp 1–8. https://doi.org/10.23919/IWLPC52010.2020.9375884
GDDR6 memory explained: what it is, and why it matters for next-gen. https://www.gamesradar.com/gddr6-memory-explained
Going beyond GPUs with GDDR6. https://www.chipestimate.com/Going-Beyond-GPUs-with-DDR6/Rambus/Technical-Article/2019/04/09
Hou F, Wang W, Lin T, Cao L, Zhang GQ, Ferreira JA (2019) Characterization of PCB embedded package materials for SiC MOSFETs. IEEE Trans Compon, Packag Manuf Technol 9: 1054–1061. https://doi.org/10.1109/TCPMT.2019.2904533
How to design your HDI PCB stackup. https://www.nwengineeringllc.com/article/how-to-design-your-hdi-pcb-stackup.php
Institute of electrical and electronics engineers (IEEE) (2022) IEEE standard for ethernet amendment 4: physical layer specifications and management parameters for 100 Gb/s, 200 Gb/s, and 400 Gb/s electrical interfaces based on 100 Gb/s signaling, In: IEEE Std 802.3ck-2022 (Amendment to IEEE Std 802.3–2022 as amended by IEEE Std 802.3dd-2022, IEEE Std 802.3cs-2022, and IEEE Std 802.3db-2022), pp 1–316. https://doi.org/10.1109/IEEESTD.2022.9999414
IEEE (2016) IEEE Standard for Ethernet. In: IEEE Std 802.3–2015 (Revision of IEEE Std 802.3–2012). USA, pp 1–4017. https://doi.org/10.1109/IEEESTD.2016.7428776
Jiang X et al (2022) 224 Gbps-PAM4 end-to-end channel solutions for high-density networking system. In: DesignCon, USA
Jiang X et al (2021) Designing 224G High performance FPGA package and board with confidence. In: DesignCon, USA
Kabat AK, Pandey S, Gopalakrishnan VT (2022) Performance evaluation of high bandwidth memory for HPC workloads. In: 2022 IEEE 35th international system-on-chip conference (SOCC). IEEE, Belfast, United Kingdom, pp 1–6. https://doi.org/10.1109/SOCC56010.2022.9908071
Kim S, Kim S, Kim H, Cho K, Kim J (2019) Design methodology of passive equalizer for GDDR6 memory test. In: 2019 joint international symposium on electromagnetic compatibility, sapporo and Asia-Pacific international symposium on electromagnetic compatibility (EMC Sapporo/APEMC). IEEE, Sapporo, Japan, pp 270–273. https://doi.org/10.23919/EMCTokyo.2019.8893936
Kim J, Noquil JA, keng Tan T, Wu C-L, Choi S-Y (2005) Multi-flip chip on lead frame overmolded IC package: a novel packaging design to achieve high performance and cost effective module package. In: Proceedings electronic components and technology, 2005. ECTC ’05. IEEE, Lake Buena Vista, FL, USA, pp 1819–1821. https://doi.org/10.1109/ECTC.2005.1442043
Lau JH (2019a) Heterogeneous integrations. Springer Singapore, Singapore
Lau JH (2019b) Recent advances and trends in heterogeneous integrations. J Microelectron Electron Packag 16:45–77. https://doi.org/10.4071/imaps.780287
Li L, Lee DW, Hwang K-P, Min Y, Wang SX (2009) On-package magnetic materials for embedded inductor applications. In: 2009 international conference on electronic packaging technology & high density packaging. IEEE, Beijing, China, pp 471–474. https://doi.org/10.1109/ICEPT.2009.5270707
Marte A, Ernst U, Wu J, Yauw O, Clauberg H, Buergi D, Chylak B, Friederichs U, Barthold U (2018) Advances in memory die stacking. In: 2018 IEEE 68th electronic components and technology conference (ECTC). IEEE, San Diego, CA, pp 407–418. https://doi.org/10.1109/ECTC.2018.00068
Mingmin Z, Donglin S, Fei D, Shenqing K, Xiaoxiao W (2006) The effect of impedance matching to high-speed connector’s signal integrity. In: 2006 7th international symposium on antennas, propagation & EM theory. IEEE, Guilin, China, pp 1–4. https://doi.org/10.1109/ISAPE.2006.353324
Muraoka S, Shinkai G, Yagyu M, Uematsu Y, Ogihara M, Sezaki N, Osaka H (2011) PCB trace modeling and equalizer design method for 10 Gbps backplane. In: 2011 IEEE electrical design of advanced packaging and systems symposium (EDAPS). IEEE, Hanzhou, pp 1–4. https://doi.org/10.1109/EDAPS.2011.6213769
Na N, To H (2019) Effectiveness of equalization and performance potential in DDR5 channels with RDIMM(s). In: 2019 IEEE 69th electronic components and technology conference (ECTC). IEEE, Las Vegas, NV, USA, pp 1208–1214. https://doi.org/10.1109/ECTC.2019.00187
Nitin B, Randy W, Shinichiro I, Eiji F, Shibata R, Yumiko S, Megumi O (2018) DDR5 design challenges. In: 2018 IEEE 22nd workshop on signal and power integrity (SPI). IEEE, Brest, pp 1–4. https://doi.org/10.1109/SaPIW.2018.8401666
Ng CS, Yeo TS (1998) Effects of interline coupling on bit error rate for high-speed digital signal propagation on PCB. IEEE Trans Ind Electron 45:362–364. https://doi.org/10.1109/41.681238
Pfahl B, Fu H, Richardson C (2012) Highlights of iNEMI 2013 technology roadmaps. In: 2012 35th IEEE/CPMT international electronics manufacturing technology conference (IEMT). IEEE, Ipoh, Perak, Malaysia, pp 1–5. https://doi.org/10.1109/IEMT.2012.6521822
Printed electronics in 2021: new applications emerging. https://screenprintingmag.com/printed-electronics-in-2021-new-applications-emerging
Printed and flexible electronics for automotive applications 2021–2031: technologies and markets. https://www.idtechex.com/en/research-report/printed-and-flexible-electronics-for-automotive-applications-2021-2031-technologies-and-markets/806
Status of The Advanced Packaging Industry (2021) https://s3.i-micronews.com/uploads/2021/09/YINTR21223-Status-of-the-Advanced-Packaging-Industry-2021-flyer.pdf
Standardizing chiplet interconnects. https://semiengineering.com/standardizing-chiplet-interconnects
Teng T, Wang M, Hsu J, Lee W, Su T, Kan J, Chen B (2022) PCIe-Express channel design optimization for out-of-guideline three connector topology. In: 2022 17th international microsystems, packaging, assembly and circuits technology conference (IMPACT). IEEE, Taipei, Taiwan, pp. 1–4. https://doi.org/10.1109/IMPACT56280.2022.9966687
Universal Chiplet Interconnect Express. https://www.uciexpress.org/why-choose-us
Vertical conductive structure a new interconnect technology. https://www.nextgin-tech.com/innovation-areas/vecs
Vertical conductive structures (VeCS) for PCB HD trace routing. https://resources.pcb.cadence.com/blog/2020-vertical-conductive-structures-vecs-for-pcb-hd-trace-routing
Wu X (2015) 3D-IC technologies and 3D FPGA. In: 2015 international 3D systems integration conference (3DIC). p. KN1.1-KN1.4. IEEE, Sendai, Japan. https://doi.org/10.1109/3DIC.2015.7334564
Wu J, Yauw O, Tan A, Clauberg H, Buergi D (2018) Thin die stacking technologies for 3D memory packages. In: 2018 China semiconductor technology international conference (CSTIC). IEEE, Shanghai, pp 1–3. https://doi.org/10.1109/CSTIC.2018.8369299
Zhang W, Li N, Kasper E, Zheng Z, Shi L (2019) Impact analysis of high-frequency material and pcb fabrication technology on antenna design for 77/79 GHz automotive radar. In: 2019 IEEE Asia-Pacific microwave conference (APMC). IEEE, Singapore, Singapore, pp 655–657. https://doi.org/10.1109/APMC46564.2019.9038424
Zhang J, Lim J, Yao W, Qiu K, Brooks R (2014) PCB via to trace return loss optimization for >25 Gbps serial links. In: 2014 IEEE international symposium on electromagnetic compatibility (EMC). IEEE, Raleigh, NC, pp 619–624. https://doi.org/10.1109/ISEMC.2014.6899045
4TH Gen AMD EPYC™ processor architecture. https://www.amd.com/system/files/documents/4th-gen-epyc-processor-architecture-white-paper.pdf
Acknowledgements
The author, Hansel Desmond D'Silva, would like to express his gratitude to his son, Howard, his wife, Chrisenn, for their encouragement and support throughout the writing of this chapter. He would also like to acknowledge his parents and godparents for instilling in him the values and wisdom that have contributed to his success and strong faith. The author Amit Kumar would like to express his gratitude to his son, Avyan, his wife, Anupriya, his parents, brother, and the entire family for always standing with him and supporting him in every phase of life.
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D’Silva, H.D., Kumar, A. (2024). Emerging Interconnect Technologies for Integrated Circuits and Flexible Electronics. In: Agrawal, Y., Mummaneni, K., Sathyakam, P.U. (eds) Interconnect Technologies for Integrated Circuits and Flexible Electronics. Springer Tracts in Electrical and Electronics Engineering. Springer, Singapore. https://doi.org/10.1007/978-981-99-4476-7_10
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