Abstract
An interconnect can be modeled as a linear RLC equivalent, and this accurate interconnect structure can be modeled by using complex and higher-order transfer functions. These complex and higher-order transfer functions generally require large resources in terms of memory and time, especially for a timing analysis tool to calculate the interconnect delay (net delay) and run time, which is very high because of higher number of poles. This chapter describes the methodology to reduce the higher-order transfer function to lower-order transfer function keeping in view that stability and response of the reduced system should be matched with the original higher-order system. The model order reduction achieves an advantage in terms of memory and time complexity. This work utilizes pole clustering and Pade's approximation techniques to reduce the order of the system.
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Mummaneni, K., Malvika, Kumar, V. (2024). An Efficient Model Order Reduction of Interconnects Using Machine Learning for Timing Analysis. In: Agrawal, Y., Mummaneni, K., Sathyakam, P.U. (eds) Interconnect Technologies for Integrated Circuits and Flexible Electronics. Springer Tracts in Electrical and Electronics Engineering. Springer, Singapore. https://doi.org/10.1007/978-981-99-4476-7_1
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DOI: https://doi.org/10.1007/978-981-99-4476-7_1
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