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Denoising of ECG Signal Using Optimized IIR Filter Architecture—A CSD-Based Design

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Advances in VLSI, Signal Processing, Power Electronics, IoT, Communication and Embedded Systems (VSPICE 2022)

Abstract

Signal Processing is a primary and important task in most of the applications involving signal acquisition and digital processing. Signal conditioning can be thought of as a process of removing unwanted information and preserving the required feature of the signal. Denoising can be similarly correlated with signal conditioning in this regard. The presented work is gives an IIR filter architecture that is optimized for area and speed metric for an end application of ECG signal processing. The proposed IIR filter uses Canonic Signed Digits (CSD) for representing scaled version of filter coefficients and then the IIR filter is designed. It is observed that by using CSD-based IIR filter architecture gives an efficient approach to denoise the ECG signals, demonstrates the area reduction by 90%, and improves the speed of operation by 60% when compared with conventional design. The Matlab and Xilinx Vivado platform is used to validate the designed IIR filter and further the post-synthesis implementation details are obtained for Xilinx Virtex-7 series XC7VX485T-2FFG1761C FPGA, Verilog HDL coding is employed to develop the design and stimulus environment for the work.

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Acknowledgements

We the authors would like to thank the management and principal of KLE Dr. M S Sheshgiri College of Engineering and Technology, Belagavi Campus, KLE Technological University, Hubballi, for encouraging us to carry out the presented work and also extend our gratitude to HOD, E&CE and Project coordinator for the kind support.

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Correspondence to Kunjan D. Shinde .

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We the authors would like to declare that there is NO Conflict of Interest on the research work presented.

NO data sets were generated or created in the process. ECG signal of record mentioned in [2] is used for the presented work.

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Shinde, K.D., Khanapure, D., Shetti, N., Athavani, J., Hattiholi, N. (2024). Denoising of ECG Signal Using Optimized IIR Filter Architecture—A CSD-Based Design. In: Kalya, S., Kulkarni, M., Bhat, S. (eds) Advances in VLSI, Signal Processing, Power Electronics, IoT, Communication and Embedded Systems. VSPICE 2022. Lecture Notes in Electrical Engineering, vol 1062. Springer, Singapore. https://doi.org/10.1007/978-981-99-4444-6_11

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  • DOI: https://doi.org/10.1007/978-981-99-4444-6_11

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