Abstract
The development of modern very large-scale integration circuits is aimed increasing the degree of integration, which will provide higher speeds. For that, it is necessary to reduce the size of all the logical elements and increase the number of metal layers, which in its turn will lead to an increase in the parasitic capacitance and inductance of the transmission lines (interconnections). As a result, we will have a signal delay in the transmission lines, which will affect the speed of the system.
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References
Kumar A (2012) Study the performance analysis of carbon nanotube as a VLSI interconnect. Patiala: Thapar University, p 101. http://hdl.handle.net/10266/1898
Jaing Y (2006) Modeling and optimization of VLSI interconnects. USA: Nevada Las Vegas. Department Elect and Computer Engineering, University of Nevada Las Vegas, p 100
The international technology roadmap for semiconductors. URL: http://www.itrs2.net (20.07.2018)
Ismail I, Friedman EG (2002) Effects of inductance on the propagation delay and repeater insertion in VLSI circuits: a summary. Circ Syst Soc Outstand Young Author Award 8(2):195–206
Abinash R, Noha M (2007) Effects of coupling capacitance and inductance on delay uncertainty and clock skew. USA: Illinois Chicago. Department of Elect. and Computer Engineering. University of Illinois at Chicago, pp 184–187
Ramadass U (2013) A novel interconnect structure for Elmore delay model with resistance – capacitance – conductance scheme/Ramadass U, Krishnappriya, J. Ponnian. Am J Appl Sci 10(8):881–892. https://doi.org/10.3844/ajassp.2013.881.892
Yang XD, Cheng CK, Ku WH et al (2002) Hurwitz stable reduced order modeling for RLC interconnect trees. IEEE J Anal Integr Circ Signal Process 31:222–228
Ismail YI (Dec. 2002) On-chip inductance cons and pros. IEEE Trans VLSI Syst 685–694
Kahng AB, Muddu S, Vidhani D (Jan 2004) Noise and delay uncertainty studies for coupled RC interconnects. In: Proceedings IEEE international conference on VLSI design, pp 431–436
Chen YH et al. (Jun. 2020) Ultra high density SoIC with sub-micron bond pitch. In: Proceedings IEEE 70th electronic components technology conference (ECTC), pp 576–581
Yan J-T, Tseng Y-J, Yen C-H (Dec. 2014) Efficient micro-bump assignment for RDL routing in 3DICs. In: Proceedings 21st IEEE international conference on electronics, circuits and systems (ICECS), pp 195–198
Panth S, Samadi K, Du Y, Lim SK (Oct. 2017) Shrunk-2-D: a physical design methodology to build commercial-quality monolithic 3-D ICs. IEEE Trans Comput Aided Design Integr Circuits Syst 36(10):1716–1724
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Avdalyan, N., Petrosyan, A. (2023). Development of a Method for Reducing the Impact of Metal Interconnection Parameters on the Speed of VLSI. In: Yang, XS., Sherratt, R.S., Dey, N., Joshi, A. (eds) Proceedings of Eighth International Congress on Information and Communication Technology. ICICT 2023. Lecture Notes in Networks and Systems, vol 694. Springer, Singapore. https://doi.org/10.1007/978-981-99-3091-3_1
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DOI: https://doi.org/10.1007/978-981-99-3091-3_1
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