Abstract
The SPI-Serial Peripheral Interface is considered as one of the most used bus protocols for attaching processors to associated devices with low/medium data transmission rates (SPI). In SoC applications, the SPI architecture is utilized to connect a large number of peripherals to the processor. The slave, which could be a sensor, monitor, or memory chip, is controlled by the master. A pre-packaged collection of code called Verification IP (VIP) is utilized for verification. A module designed to be used with a certain verification methodology, like UVM, may be the object at hand. Alternatively, it may be a set of statements for validating a bus protocol. The objective of the project is to provide Verification IP (VIP) blocks for an SPI controller coupled to an open POWER CPU, fabless SoC with an A2O core, utilizing the AXI4 interface. By creating test benches in UVM and System Verilog, the SPI controller’s verification and VIP development are carried out. Software from Mentor Graphics® and Xilinx Vivado® was used for the simulation, synthesis, and verification, respectively.
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Anu Priya, D., Vishnuvardhan, D., Mamatha, G., Shaik, F., Karimullah, S. (2023). VIP Development of SPI Controller for Open-Power Processor-Based Fabless SOC. In: Kumar, A., Ghinea, G., Merugu, S. (eds) Proceedings of the 2nd International Conference on Cognitive and Intelligent Computing. ICCIC 2022. Cognitive Science and Technology. Springer, Singapore. https://doi.org/10.1007/978-981-99-2742-5_2
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DOI: https://doi.org/10.1007/978-981-99-2742-5_2
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