Cell Optimization and Realization of XOR-Based Logic Design in QCA

Abstract

Quantum-Dot Cellular Automata is a recently introduced technology which is having a tremendous amount of potential to replace conventional CMOS technology for implementing various digital logic circuits because of its remarkable features like reduced area, less power consumption, high processing speed, etc. In this article, efficient 2-Input and 3-Input QCA XOR and XNOR gates are designed with a minimum number of cells and compared to previously proposed designs. To check the effectiveness of these proposed XOR and XNOR gates, we further use them to design a 1-bit Full Adder circuit with reduced number of cells. The proposed XOR and XNOR gates were further used to design QCA-based Even Parity Generator circuit and Odd Parity Generator circuit. These generator circuits are highly efficient in terms of area consumed since it uses minimum number of cells to get the expected output. The proposed design of 2-Input XOR and XNOR, and 3-Input XOR and XNOR logic gates have yielded 60.00, 38.46, 71.42, and 66.67% reductions in the number of cells used to form the circuit, respectively. In comparison with previously proposed circuits, it was also observed that there is a 36.84% reduction in the cell count of the proposed Full Adder circuit, 81.48, 78.57, 79.07, and 78.40% reductions in the cell count of the newly proposed three-bit and four-bit Even Parity Generator and Odd Parity Generator, respectively. QCA Designer software is used for calculating the various parameters like cell count, clock latency, and cost of the proposed design.