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Performance Analysis of Various Charge Pump Topologies for PLL Application

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VLSI, Communication and Signal Processing (VCAS 2022)

Part of the book series: Lecture Notes in Electrical Engineering ((LNEE,volume 1024))

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Abstract

This article includes various CMOS charge pump (CP) circuits used in high-performance PLL. High-performance CP signifies the one having lowest current mismatch, wider matching range, low power dissipation along with good noise performance. This article analyzes seven different topologies of charge pump classic current steering charge pump, two stage charge pump, NMOS switch charge pump, OPAMP-based charge pump, compensation speed charge pump, self cascode-based charge pump, and double-ended CP. This study signifies that the charge pump circuits are a heart of PLL and exhibit a significant role in the performance of the PLL. Thus, a comparative study has been conducted to select a charge pump design among various available designs based on specific application. Based on the comparative study, conclusion is made that the two-stage charge pump has the highest power dissipation with 1.8mW and the double-ended charge pump consume least power with a reduction of 99%. Two stage gives maximum matching of output voltage, i.e., 70% of supply voltage. OPAMP-based and double-ended charge pump provides least-current mismatch of less than 1%.

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Acknowledgements

The authors are grateful to their college IET Lucknow, for providing the cadence virtuoso software in their lab.

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Authors and Affiliations

  1. Electronics and Communication Department, IET Lucknow, Lucknow, India

    Nashra Khalid & Ram Chandra Singh Chauhan

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  1. Nashra Khalid
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  2. Ram Chandra Singh Chauhan
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Corresponding author

Correspondence to Nashra Khalid .

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Editors and Affiliations

  1. Department of Electronics and Communication Engineering, Motilal Nehru National Institute of Technology Allahabad, Prayagraj, Uttar Pradesh, India

    R. K. Nagaria

  2. Department of Electronics and Communication Engineering, Motilal Nehru National Institute of Technology Allahabad, Prayagraj, Uttar Pradesh, India

    V. S. Tripathi

  3. Department of Electrical, Electronic and Communications Engineering, Public University of Navarra (UPNA), Pamplona, Spain

    Carlos Ruiz Zamarreno

  4. Department of Electronics and Communication Engineering, Motilal Nehru National Institute of Technology Allahabad, Prayagraj, Uttar Pradesh, India

    Yogendra Kumar Prajapati

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Khalid, N., Chauhan, R.C.S. (2023). Performance Analysis of Various Charge Pump Topologies for PLL Application. In: Nagaria, R.K., Tripathi, V.S., Zamarreno, C.R., Prajapati, Y.K. (eds) VLSI, Communication and Signal Processing. VCAS 2022. Lecture Notes in Electrical Engineering, vol 1024. Springer, Singapore. https://doi.org/10.1007/978-981-99-0973-5_25

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  • DOI: https://doi.org/10.1007/978-981-99-0973-5_25

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  • Publisher Name: Springer, Singapore

  • Print ISBN: 978-981-99-0972-8

  • Online ISBN: 978-981-99-0973-5

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