Skip to main content
SpringerLink
Log in

Design of a Low-Power Varactor-Based DCO Using NMOS Switching Network as a Digital Control Technique

  • Conference paper
  • First Online:
Evolution in Signal Processing and Telecommunication Networks (ICMEET 2023)

Part of the book series: Lecture Notes in Electrical Engineering ((LNEE,volume 1155))

  • 49 Accesses

Abstract

This paper introduces a new design of a varactor-based Digitally Controlled Oscillator (DCO). The hybrid ring-type DCO is designed using three different delay stages. Each delay stage consists of a varactor-based load element which is controlled digitally using an NMOS-based switching network. A 4-bit three-stage DCO and a 4-bit five-stage DCO have been designed, both utilizing the MOS varactor as a load element. The 4-bit three-stage DCO exhibits a frequency variation from 2.092 to 1.750 GHz while consuming 0.643 mW of power. In the case of a 4-bit five-stage DCO, the output frequency is in the range of 1.080–0.920 GHz, accompanied by a power consumption of 1.099 mW. The control bits are systematically changed from [0000] to [1111]. The effects of varying supply voltage on the output frequency and power consumption are also measured and recorded. Results are obtained in TSMC 0.18 µm CMOS process technology.

This is a preview of subscription content, log in via an institution to check access.

Access this chapter

Log in via an institution
Chapter
USD 29.95
Price excludes VAT (USA)
  • Available as PDF
  • Read on any device
  • Instant download
  • Own it forever
eBook
USD 229.00
Price excludes VAT (USA)
  • Available as EPUB and PDF
  • Read on any device
  • Instant download
  • Own it forever
Hardcover Book
USD 299.99
Price excludes VAT (USA)
  • Durable hardcover edition
  • Dispatched in 3 to 5 business days
  • Free shipping worldwide - see info

Tax calculation will be finalised at checkout

Purchases are for personal use only

Institutional subscriptions

References

  1. Lee S, Kim B, Lee K (1997) A novel high-speed ring oscillator for multiphase clock generation using negative skewed delay scheme. IEEE J Solid State Circuits 32(2):289–291. https://doi.org/10.1109/4.551926

    Article  Google Scholar 

  2. Catli B, Hella MM (2008) A 0.5-V 3.6/5.2 GHz CMOS multi-band LC VCO for ultra low-voltage wireless applications. In: 2008 IEEE international symposium on circuits and systems, Seattle, WA, USA, pp 996–999. https://doi.org/10.1109/ISCAS.2008.4541588

  3. Sheng D, Chung C-C, Lee C-Y (2007) An ultra-low-power and portable digitally controlled oscillator for SoC applications. IEEE Trans Circuits Syst II Express Briefs 54(11):954–958. https://doi.org/10.1109/TCSII.2007.903782

    Article  Google Scholar 

  4. Dunning J, Garcia G, Lundberg J, Nuckolls E (1995) An all-digital phase-locked loop with 50-cycle lock time suitable for high-performance microprocessors. IEEE J Solid-State Circuits 30(4):412–422. https://doi.org/10.1109/4.375961

    Article  Google Scholar 

  5. Olsson T, Nilsson P (2004) A digitally controlled PLL for SoC applications. IEEE J Solid-State Circuits 39(5):751–760. https://doi.org/10.1109/JSSC.2004.826333

    Article  Google Scholar 

  6. Chung C-C, Lee C-Y (2003) An all-digital phase-locked loop for high-speed clock generation. IEEE J Solid-State Circuits 38(2):347–351. https://doi.org/10.1109/JSSC.2002.807398

    Article  Google Scholar 

  7. Sheng D, Chung C-c, Lee C-y (2006) An all-digital phase-locked loop with high-resolution for SoC applications. In: Proceedings of the international symposium on VLSI design, automation and test, Hsinchu, Taiwan, pp 1–4. https://doi.org/10.1109/VDAT.2006.258161

  8. Staszewski RB, Balsara PT (2007) All-digital PLL with ultra fast settling. IEEE Trans Circuits Syst II Express Briefs 54(2):181–185. https://doi.org/10.1109/TCSII.2006.886896

    Article  Google Scholar 

  9. Staszewski RB, Hung C-M, Leipold D, Balsara PT (2003) A first multigigahertz digitally controlled oscillator for wireless applications. IEEE Trans Microwave Theory Tech 51(11):2154–2164. https://doi.org/10.1109/TMTT.2003.818579

  10. Wang S, Quan J, Luo R, Cheng H, Yang H (2007) A noise reduced digitally controlled oscillator using complementary varactor pairs. In: 2007 IEEE international symposium on circuits and systems, New Orleans, LA, USA, pp 937–940. https://doi.org/10.1109/ISCAS.2007.378080

  11. Staszewski RB, Hung C-M, Barton N, Lee M-C, Leipold D (2005) A digitally controlled oscillator in a 90 nm digital CMOS process for mobile phones. In IEEE J Solid-State Circ 40(11):2203–2211. https://doi.org/10.1109/JSSC.2005.857359

  12. Olsson T, Nilsson P (2003) Portable digital clock generator for digital signal processing applications. Electron Lett 39:1372–1374. https://doi.org/10.1049/el:20030910

    Article  Google Scholar 

  13. Chung Y-M, Wei C-L (2009) An all-digital phase-locked loop for digital power management integrated chips. In: 2009 IEEE international symposium on circuits and systems, Taipei, Taiwan, pp 2413–2416. https://doi.org/10.1109/ISCAS.2009.5118287

  14. Dwivedi D, Kumar M (2019) Design of a 3-bit digital control oscillator (DCO) using IMOS varactor tuning. Analog Integr Circ Sig Process 100(3):613–620. https://doi.org/10.1007/s10470-019-01506-x

    Article  Google Scholar 

  15. Kumar M (2013) A low power voltage controlled oscillator design. ISRN Electron 2013:Article ID 987179, 6 p. https://doi.org/10.1155/2013/987179

  16. Upadhyay H, Choubey A, Nigam K (2012) Comparison among different CMOS inverter with stack keeper approach in VLSI design. Int J Eng Res Appl (IJERA) 2(3):640–646. ISSN: 2248-9622

    Google Scholar 

  17. Pokharel RK, Tomar A, Kanaya H, Yoshida K (2008) Design of highly linear: 1 GHz 8-bit digitally controlled ring oscillator with wide tuning range in 0.18 μm CMOS process. In: 2008 China–Japan joint microwave conference, Shanghai, China, pp 623–626. https://doi.org/10.1109/CJMW.2008.4772508

  18. Yoshida T, Ishida N, Sasaki M, Iwata A (2007) Low-voltage, low-phase-noise ring voltage-controlled oscillator using 1/f-noise reduction techniques. Jpn J Appl Phys 46(4S):2257–2260. https://doi.org/10.1143/JJAP.46.2257

  19. Tomar A, Pokharel RK, Nizhnik O, Kanaya H, Yoshida K (2007) Design of 1.1 GHz highly linear digitally-controlled ring oscillator with wide tuning range. In: IEEE international workshop on radio-frequency integration technology, Singapore, pp 82–85. https://doi.org/10.1109/RFIT.2007.4443926

  20. Sheu ML, Tiao YS, Taso LJ (2011) A 1-V 4-GHz wide tuning range voltage-controlled ring oscillator in 0.18 μm CMOS. Microelectron J 42(6):897–902. https://doi.org/10.1016/j.mejo.2011.03.015

  21. Dwivedi D, Kumar M, Niranjan V (2021) Design of power-efficient CMOS based oscillator circuit with varactor tuning control. SN Appl Sci 3(4):487. https://doi.org/10.1007/s42452-021-04501-y

    Article  Google Scholar 

Download references

Author information

Authors and Affiliations

  1. USIC&T, GGSIPU, Delhi, India

    Shweta Dabas & Shweta Dabas

  2. National Institute of Technology, Delhi, India

    Manoj Kumar

Authors
  1. Shweta Dabas
    View author publications

    You can also search for this author in PubMed Google Scholar

  2. Manoj Kumar
    View author publications

    You can also search for this author in PubMed Google Scholar

Corresponding author

Correspondence to Shweta Dabas .

Editor information

Editors and Affiliations

  1. Department of Electronics Engineering, Faculty of Engineering and Technology, Veer Bahadur Singh Purvanchal University, Jaunpur, Uttar Pradesh, India

    Vikrant Bhateja

  2. Department of Electronics and Communication Engineering, Raghu Institute of Technology, Visakhapatnam, Andhra Pradesh, India

    P. Satish Rama Chowdary

  3. Autonomous University of Baja California, Mexicali, Baja California, Mexico

    Wendy Flores-Fuentes

  4. Department of Electrical Engineering, College of Engineering, Princess Nourah bint Abdulrahman University, Riyadh, Saudi Arabia

    Shabana Urooj

  5. Department of Electronics and Communication Engineering, National Institute of Technology Mizoram, Aizawl, India

    Rudra Sankar Dhar

Rights and permissions

Reprints and permissions

Copyright information

© 2024 The Author(s), under exclusive license to Springer Nature Singapore Pte Ltd.

About this paper

Check for updates. Verify currency and authenticity via CrossMark

Cite this paper

Dabas, S., Kumar, M. (2024). Design of a Low-Power Varactor-Based DCO Using NMOS Switching Network as a Digital Control Technique. In: Bhateja, V., Chowdary, P.S.R., Flores-Fuentes, W., Urooj, S., Sankar Dhar, R. (eds) Evolution in Signal Processing and Telecommunication Networks. ICMEET 2023. Lecture Notes in Electrical Engineering, vol 1155. Springer, Singapore. https://doi.org/10.1007/978-981-97-0644-0_13

Download citation

  • DOI: https://doi.org/10.1007/978-981-97-0644-0_13

  • Published:

  • Publisher Name: Springer, Singapore

  • Print ISBN: 978-981-97-0643-3

  • Online ISBN: 978-981-97-0644-0

  • eBook Packages: EngineeringEngineering (R0)

Publish with us

Policies and ethics

Search

Navigation