Direct Digital Synthesizer Based Clock Source for ADC Sampled System
In this paper a Direct Digital Synthesizer (DDS) clock source application in sampled system is proposed. It is used to replace the analog Phase-Locked Loop (PLL) of a multi-formats test set that supports wireless mobile telecommunication. The DDS in this work operates from 1 μHz to 150 MHz with utilization range of 2.5–40 MHz. The rms jitter is less than 8 ps and peak jitter less than 20 ps for a reference clock signal of 20 MHz. From result, the design achieves phase noise less than −100 dBc/Hz at 1 kHz offset. It also demonstrates a total cost reduction of 61 % as compared to analog PLL implementation.
KeywordsDDS PLL Clock source Phase noise Jitter
The authors would like to thank the Agilent Technologies and Universiti Sains Malaysia in supporting the carried out research investigation.
- 1.Kern P (2007) Direct digital synthesis enables digital PLLs. RF Des 3(33):26–30Google Scholar
- 2.Fang Y-Y, Chen X-J (2011) Design and simulation of DDS based on quartus II. In: IEEE international conference on computer science and automation engineering (CSAE), 10–12 June, pp 357–360Google Scholar
- 3.Stanford Research System (2013) Direct digital synthesis. Application Note, pp 1–5Google Scholar
- 4.Vankka J, Halonen KAI (2001) Direct digital synthesizer theory, design and application. Springer, LondonGoogle Scholar
- 5.Kester W (2008) Converting phase noise to time jitter. Analog Devices. MT-008 (Rev. A), 1–10Google Scholar
- 6.Yannick G, Enrico R (2012) Phase noise and amplitude noise in DDS. In: IEEE international conference on frequency control symposium (FCS), pp 1–6Google Scholar
- 7.Romashov VV, Romashova LV, Khramov KK (2011) Research of phase noise of direct digital synthesizers. In: International Siberian conference on control and communications (SIBCON2011), Krasnoyarsk, pp 168–171Google Scholar