Power Efficient Magnitude Comparator Using Adiabatic Logic and Gate Diffusion Technique

Abstract

In the advanced technology, designing of low power, high speed portable devices is a challenging issue. Power dissipation can be minimized by using adiabatic logic style. In compared to gate diffusion input technique, an adiabatic logic required more number of transistors, and more power is needed. This paper demonstrates the design and implementation of 2-bit magnitude comparator using different adiabatic logic styles and comparing with the gate diffusion input technique in terms of power consumption and transistor count. The simulation has been done by using the DSCH and Microwind software.