Abstract
In the present scenario, power consumption is a vital issue in low power circuit design. The adiabatic logic and the conventional CMOS logic styles are widely used in low power VLSI design. The power saving is more effective in adiabatic circuit compared to conventional CMOS logic. In compared to gate diffusion technique, an adiabatic logic required more number of transistors, and more power is needed. The objective of this paper is to design and implement of 4:1 multiplexer using different adiabatic logic styles and gate diffusion technique and compares them in terms of the power dissipation and transistor count. The simulation has been done by using the EDA Tanner tools.
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Mukherjee, D.N., Biswas, S., Panda, S., Maji, B. (2021). Performance Analysis of Multiplexer Using Adiabatic Logic and Gate Diffusion Technique. In: Mukherjee, M., Mandal, J., Bhattacharyya, S., Huck, C., Biswas, S. (eds) Advances in Medical Physics and Healthcare Engineering. Lecture Notes in Bioengineering. Springer, Singapore. https://doi.org/10.1007/978-981-33-6915-3_20
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DOI: https://doi.org/10.1007/978-981-33-6915-3_20
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