Abstract
The data stability issues in SRAM cells become more prominent with the decreasing of feature sizes in CMOS technology. The focus of memory manufacturers always remains on reducing power consumption and stability improvements of the SRAM cells. In this work, the critical parameters of FinFET and CMOS transistors based on SRAM cells are compared. This paper focuses on the simulation of 10T SRAM cell topologies design using sleep transistor, drowsy cache, and self-controllable voltage technique (SVL) techniques and their comparison. Among all these techniques, SVL shows the best results by consuming 4768 nw power for FinFET technology and 15.8383 n W power for CMOS technology. Evaluated results show 40%, 26%, and 10% improvement in HSNM, RSNM, and WSNM, respectively, and 80.93% reduction in leakage power. FinFET design SRAM cells result in higher RSNM, HSNM, and WSNM. For simulation, the HSPICE tool is used at 32 nm PTM CMOS and FinFET transistor with a supply voltage of 900 mV and 25 °C temperature.
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Sharma, D., Birla, S. (2021). Comparative Study of CMOS and FinFET-Based SRAM Cell Using SVL Technique. In: Sharma, D.K., Son, L.H., Sharma, R., Cengiz, K. (eds) Micro-Electronics and Telecommunication Engineering. Lecture Notes in Networks and Systems, vol 179. Springer, Singapore. https://doi.org/10.1007/978-981-33-4687-1_2
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DOI: https://doi.org/10.1007/978-981-33-4687-1_2
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