Design Constraints and SDC Commands

Abstract

The important design constraints are the optimization constraints and the design rule constraints. Using Synopsys Design Compiler (Synopsys DC), we can optimize for the speed and area and the power planning, DRC is checked during the physical design phase. The design has clean timing indicates that the design meets all the required constraints, the constraints can be block level, top level, and chip level, and meeting these constraints during various ASIC design phases indicates the design is ready to manufacture. The chapter discusses these constraints and the important SDC commands, where SDC stands for the Synopsys Design Compiler which is a powerful ASIC synthesis tool.

Design optimization constraints are speed, area, and power.