Abstract
An adder can be treated as a fundamental component to perform arithmetic operations. A large number of operations can be performed by using adders such as additions, subtractions, multiplications, and divisions. In this paper two structures for hybrid CSA-CIA adder were proposed. This paper gives a comparative study of existing hybrid CSA-CIA adder and proposed hybrid CSA-CIA adders. The existing CSA-CIA hybrid adder does not work for all the combinations of inputs. The proposed designs work good for all input combinations. Also the proposed hybrid CSA-CIA adder2 has less energy and delay values compared to existing CSA-CIA hybrid adder. The code is written in Verilog hardware description language (HDL) and the simulations done by using Cadence Nclaunch tool. The layout reports are generated using Cadence Encounter tool.
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Tatiknoda, G.D., Thummala, K., Neelam, A.K., Musala, S. (2021). Energy Efficient and Accurate Hybrid CSA-CIA Adders. In: Laxminidhi, T., Singhai, J., Patri, S.R., Mani, V.V. (eds) Advances in Communications, Signal Processing, and VLSI. Lecture Notes in Electrical Engineering, vol 722. Springer, Singapore. https://doi.org/10.1007/978-981-33-4058-9_25
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DOI: https://doi.org/10.1007/978-981-33-4058-9_25
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