Abstract
This paper presents an operational-transconductance-amplifier (OTA) for ultra-low power applications with high CMRR (common mode rejection ratio) and PSRR (power supply rejection ratio). The proposed OTA is a three-stage design. In order to attain the lower supply voltage and high CMRR, a bulk-driven differential pair with the tail current source has been considered as the first stage. The current mirror biasing technique makes sure that all the transistors operate in subthreshold region. A common source amplifier has been opted with current mirror as a load in second stage. At last, common source inverting amplifier is third stage of the designed OTA. The circuit has been designed and synthesized using cadence virtuoso simulator in 180 nm CMOS technology. It has been found that these stages are helpful in achieving high low-frequency gain. Hence, CMRR and PSRR also increase in significant amount. The results describe that the proposed design offers low-frequency gain of 58 dB with CMRR of 72 dB and PSRR of 56 dB for a supply voltage (\( V_{DD} \)) of 0.5 V. The proposed OTA provides the power dissipation of 1.8 µW at \( V_{DD} \) = 0.5 V. Also, the low-frequency gain of 57 dB, CMRR of 70 dB and PSRR of 55 dB with a power dissipation of 2.5 µW have been measured at \( V_{DD} \) = 0.6 V.
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Manikanta, G., Mishra, R.A., Srivastava, N.A., Jaiswal, R.K. (2020). Design and Analysis of Self-biased OTA for Low-Power Applications. In: Dutta, D., Kar, H., Kumar, C., Bhadauria, V. (eds) Advances in VLSI, Communication, and Signal Processing. Lecture Notes in Electrical Engineering, vol 587. Springer, Singapore. https://doi.org/10.1007/978-981-32-9775-3_57
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DOI: https://doi.org/10.1007/978-981-32-9775-3_57
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