Investigating the Role of Parasitic Resistance in a Class of Nanoscale Interconnects

  • Shah Zahid YousufEmail author
  • Anil Kumar Bhardwaj
  • Rohit Sharma
Conference paper
Part of the Communications in Computer and Information Science book series (CCIS, volume 1066)


In nanoscale interconnects parasitic components are becoming drastically important with geometrical scaling. This work presents a comprehensive study of copper (Cu), SWCNT bundle, MWCNT, SC-MLGNR and TC-MLGNR nano interconnect in deep submicron (DSM) regime. We have extracted parasitic resistance of the above mentioned interconnects using physics based equivalent circuit models and investigated the effective resistivity of these interconnects at different technology nodes in DSM regime. It must be noted that when the dimensions of interconnect follow nanoscale, resistivity becomes the function of grain size. The nanoscale dimensions result in edge scattering and grain boundary scattering which inculcates tremendous effect on effective MFP. We examined the effect of grain size in scaled interconnects and analyzed the effect of edge and grain boundary scattering on resistivity of nanoscale interconnect. In our work we have look over five different interconnect geometries for the parasitic resistive component at 7 nm node and 14 nm node. We take Cu as a reference interconnect in our analysis. Our analysis show that the parasitic resistance of SWCNT Bundle, MWCNT, TC-MLGNR, SC-MLGNR interconnect is reduced by 77%, 84%, 59%, 80% compared to Cu interconnect at 7 nm node respectively. Our results also indicate a decrease of parasitic resistance by 70%, 80%, 35%, 60% compared to Cu interconnect at 14 nm node respectively. These calculations are valid below width of 14 nm. In this paper we have presented some Graphene counter parts which make it more promising candidate than CNT bundle interconnect apart from having greater p.u.l. resistance. We have analyzed the effects of Fermi energy and width on number of conduction channels for different technology nodes. This paper also shows comparable resistance of MWCNT and SWCNT due to reduced MFP of former interconnect.


Chip-to-chip interconnects Deep sub-micron (DSM) regime Multilayer Graphene Nano-ribbon (MLGNR) Parasitic resistive parameter Side-contact MLGNR (SC-MLGNR) Top-contact MLGNR (TC-MLGNR) Mean free path (MFP) Edge scattering Grain size 



The authors gratefully acknowledge the help received from Vipul Kumar Nishad during our technical discussions.


  1. 1.
    Nishad, A.K., Sharma, R.: Analytical time-domain models for performance optimization of multilayer GNR interconnects. IEEE J. Sel. Top. Quantum Electron. 20(1), 17–24 (2013)CrossRefGoogle Scholar
  2. 2.
    Zhao, W.S.: Electrical modeling of on-chip cu-graphene heteriogenious interconnects. IEEE Electron Device Lett. 36(1), 74–76 (2015)CrossRefGoogle Scholar
  3. 3.
    Lo, C.L., et al.: Studies of two dimensional h-BN and Mo S2 for potential diffusion barrier application in copper interconnect technology. NPJ 2D Matter. Appl. 1, 42 (2017)Google Scholar
  4. 4.
    Nishad, A.K., Sharma, R.: Lithium-intercalated graphene interconnects: prospects for on-chip applications. IEEE J. Electron Devices Soc. 4(6), 485–489 (2016)CrossRefGoogle Scholar
  5. 5.
    Naeemi, A., Meindl, J.D.: Compact physics based models for graphene nanoribbon interconnects. IEEE Trans. Electron Devices 56(9), 1822–1833 (2009)CrossRefGoogle Scholar
  6. 6.
    Zhao, W.S.: Verticle graphene nanoribbon interconnect at the end of the roadmap. IEEE Trans. Electron Devices 65(6), 2632–2637 (2018)CrossRefGoogle Scholar
  7. 7.
    Farahani, E.K.: Design of n-tier multilevel interconnect architectures by using carbon nanotube interconnects. IEEE Trans. VLSI Syst. 23(10), 2128–2134 (2015)CrossRefGoogle Scholar
  8. 8.
    Rakheja, S., et al.: Evaluation of the potential performance of graphene nanoribbons as on-chip interconnects. In: IEEE Proceedings, vol. 101, no. 7, pp. 1740–1764, July 2013CrossRefGoogle Scholar
  9. 9.
    Banerjee, K., et al.: Are carbon nanotubes the future of VLSI interconnects. In: DAC, vol. 47, no. 2, pp. 809–814 (2006)Google Scholar
  10. 10.
    Avouris, P., et al.: Carbon based electronics. Nat. Nanotechnol. PP, 605–615 (2005)Google Scholar
  11. 11.
    Li, H., et al.: Carbon nanomaterial for next generation interconnects and passives. IEEE Trans. Electron Devices 56, 1799–1821 (2009)CrossRefGoogle Scholar
  12. 12.
    International Technology Roadmap For Semiconductors (2013).
  13. 13.
    Steinhogl, W., et al.: Comprehensive study of the resistivity of copper wires with lateral dimensions of 100 nm and smaller. J. Appl. Phys. 97(2), 023706-1–023706-7 (2005)CrossRefGoogle Scholar
  14. 14.
    Im, S., et al.: Scaling analysis of multi-level interconnect temperatures for high performance ICs. IEEE Trans. Electron Devices 52(12), 2710–2719 (2005)CrossRefGoogle Scholar
  15. 15.
    Xu, C.: Modeling analysis and design of graphene nanoribbon interconnects. IEEE Trans. Electron Devices 56, 1567–1572 (2009)CrossRefGoogle Scholar
  16. 16.
    Kumar, V.: Performance and energy-per-bit modeling of multilayer graphene nanoribbon conductors. IEEE Trans. Electron Device 59, 904–915 (2012)CrossRefGoogle Scholar
  17. 17.
    Jiang, J., et al.: Intercalation doped multilayer graphene nanoribbons for next generation interconnects. Nano Lett. 17, 1482–1488 (2017)CrossRefGoogle Scholar
  18. 18.
    Kumar, R., et al.: Performance analysis of top-contact MLGNR based interconnect. In: IEEE Symposium on Nanoelectronic and Information System, pp. 11–16 (2016)Google Scholar
  19. 19.
    Nasiri, S.H., et al.: Compact formulae for number of conduction channels in various types of graphene nanoribbons at various temperatures. Mod. Phys. Lett. B 26(1), 1150004 1-5 (2012)CrossRefGoogle Scholar
  20. 20.
    Srivastava, N.: On the applicability of single-walled carbon nanotubes as VLSI interconnects. IEEE Trans. Nanotechnol. 8(4), 542–559 (2009)CrossRefGoogle Scholar
  21. 21.
    Sarto, M.S., Tamburrano, A.: Single-conductor transmission-line model of multiwall carbon nanotubes. IEEE Trans. Nanotechnol. 9(1), 82–92 (2010)CrossRefGoogle Scholar

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© Springer Nature Singapore Pte Ltd. 2019

Authors and Affiliations

  • Shah Zahid Yousuf
    • 1
    Email author
  • Anil Kumar Bhardwaj
    • 1
  • Rohit Sharma
    • 2
  1. 1.School of Electronics and CommunicationShri Mata Vaishno Devi UniversityKatraIndia
  2. 2.Department of Electrical EngineeringIndian Institute of Technology RoparRupnagarIndia

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