Abstract
This paper proposes an efficient closely-coupled method for integrating the widely used Advanced Encryption Standard (AES) hardware as a coprocessor IP core in the LEON3 processor-based System-on-Chip (SoC) design. As AES is increasingly being used in Internet of Things (IoT) and Edge computing devices to secure transmission of sensitive data, this method can be used to reduce the energy consumption in embedded applications. The closely-coupled method presented in this paper combines the benefits of both the traditional tightly-coupled and the industry prevalent bus-coupled approaches. The proposed method provides higher performance along with portability, to address the demand of higher processing power and reduced time-to-market. A maximum of 10% reduction in number of clock cycles was achieved in our experiments which translates to significant energy saving compared to industry prevalent bus-coupled hardware coupling method.
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Acknowledgement
We would like to thank Director CSIR-CEERI for providing the requisite lab facilities to carry out the presented work. We would also like to acknowledge the MeitY sponsored SMDP-C2SD program for providing the required CAD tools and FPGA boards.
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Bansal, R., Karmakar, A. (2019). Efficient Closely-Coupled Integration of AES Coprocessor with LEON3 Processor. In: Sengupta, A., Dasgupta, S., Singh, V., Sharma, R., Kumar Vishvakarma, S. (eds) VLSI Design and Test. VDAT 2019. Communications in Computer and Information Science, vol 1066. Springer, Singapore. https://doi.org/10.1007/978-981-32-9767-8_30
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