Abstract
Internet of Things (IoT) is now a growing part of our life. More than 10 billion devices are already connected, and more are expected to be deployed in the next coming years. To provide a practical solution for security, privacy and trust is the main concern for deploying IoT in such a large scale. For security and privacy in IoT, cryptography is the required solutions. AES algorithm is a well known, highly secure and symmetric key algorithm, but the area and power budget of AES makes it unsuitable for IoT Security. In this paper, we have presented a lightweight implementation of AES, with dual-edge triggered S-box. The proposed architecture has been implemented on FPGA as well as in ASIC on 180 nm technology. The proposed architecture uses a 32-bit data path to encrypt 128-bit plain-text with 128-bit cipher-key. ASIC implementation of the proposed architecture results in low-power (122.7 \(\upmu \)W at 1 V) consumption with a reduction in the hardware overhead by 30% and a throughput of 23 Mbps at 10 MHz clock frequency.
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References
Zanella, A., Bui, N., Castellani, A., Vangelista, L., Zorzi, M.: Internet of things for smart cities. IEEE Internet Things J. 1(1), 22–32 (2014)
Sadeghi, A.R., Wachsmann, C., Waidner, M.: Security and privacy challenges in industrial internet of things. In: Proceedings of the 52nd Annual Design Automation Conference, p. 54. ACM (2015)
Halak, B., Murphy, J., Yakovlev, A.: Power balanced circuits for leakage-power-attacks resilient design. In: Science and Information Conference (SAI), pp. 1178–1183. IEEE (2015)
Xu, T., Wendt, J.B., Potkonjak, M.: Security of IoT systems: design challenges and opportunities. In: Proceedings of the 2014 IEEE/ACM International Conference on Computer-Aided Design, pp. 417–423. IEEE Press (2014)
Sicari, S., Rizzardi, A., Grieco, L.A., Coen-Porisini, A.: Security, privacy and trust in Internet of Things: the road ahead. Comput. Netw. 76, 146–164 (2015)
Vahedi, E., Ward, R.K., Blake, I.F.: Security analysis and complexity comparison of some recent lightweight RFID protocols. In: Herrero, Á., Corchado, E. (eds.) CISIS 2011. LNCS, vol. 6694, pp. 92–99. Springer, Heidelberg (2011). https://doi.org/10.1007/978-3-642-21323-6_12
Daemen, J., Rijmen, V.: Aes proposal: Rijndael (1999)
Bui, D.H., Puschini, D., Bacles-Min, S., Beigné, E., Tran, X.T.: AES datapath optimization strategies for low-power low-energy multisecurity-level internet-of-things applications. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 25(12), 3281–3290 (2017)
Hildebrandt, R.: The Pseudo Dual-Edge D-Flipflop. http://www.ralf-hildebrandt.de/publication/publication.html. Accessed 02 June 2019
Dennard, R.H., Gaensslen, F.H., Yu, H.N., Rideout, V.L., Bassous, E., LeBlanc, A.R.: Design of ion-implanted MOSFET’s wi th very small physical dimensions. IEEE J. Solid-State Circ.SC-9(5), 256–268 (1974)
Banik, S., Bogdanov, A., Regazzoni, F.: Exploring energy efficiency of lightweight block ciphers. In: Dunkelman, O., Keliher, L. (eds.) SAC 2015. LNCS, vol. 9566, pp. 178–194. Springer, Cham (2016). https://doi.org/10.1007/978-3-319-31301-6_10
Zhang, Y., Yang, K., Saligane, M., Blaauw, D., Sylvester, D.: A compact 446 Gbps/W AES accelerator for mobile SoC and IoT in 40 nm. In: 2016 IEEE Symposium on VLSI Circuits (VLSI-Circuits), pp. 1–2. IEEE (2016)
Zhao, W., Ha, Y., Alioto, M.: AES architectures for minimum-energy operation and silicon demonstration in 65 nm with lowest energy per encryption. In: 2015 IEEE International Symposium on Circuits and Systems (ISCAS), pp. 2349–2352. IEEE (2015)
Mathew, S., et al.: 53 Gbps native GF (2 4) 2 composite-field AES-encrypt/decrypt accelerator for content-protection in 45 nm high-performance microprocessors. In: 2010 IEEE Symposium on VLSI Circuits (VLSIC), pp. 169–170. IEEE (2010)
Acknowledgment
The authors would like to thank UGC, Govt. of India under the JRF Scheme for providing financial support (Ref. No. 3548/NET-DEC. 2015). We also extend our sincere gratitude to SMDP-C2SD programme, sponsored by MeitY, Govt. of India providing the required tools to carry out this work and Semiconductor Laboratory (SCL), India for providing PDK.
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Khan, S., Gupta, N., Vishvakarma, A., Chouhan, S.S., Pandey, J.G., Vishvakarma, S.K. (2019). Dual-Edge Triggered Lightweight Implementation of AES for IoT Security. In: Sengupta, A., Dasgupta, S., Singh, V., Sharma, R., Kumar Vishvakarma, S. (eds) VLSI Design and Test. VDAT 2019. Communications in Computer and Information Science, vol 1066. Springer, Singapore. https://doi.org/10.1007/978-981-32-9767-8_26
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DOI: https://doi.org/10.1007/978-981-32-9767-8_26
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